/* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ /* FILE POLICY AND INTENDED USAGE: * This module implements functionality for training DPIA links. */ #include "link_dp_training_dpia.h" #include "dc.h" #include "inc/core_status.h" #include "dpcd_defs.h" #include "link_dp_dpia.h" #include "link_hwss.h" #include "dm_helpers.h" #include "dmub/inc/dmub_cmd.h" #include "link_dpcd.h" #include "link_dp_phy.h" #include "link_dp_training_8b_10b.h" #include "link_dp_capability.h" #include "dc_dmub_srv.h" #define DC_LOGGER … /* The approximate time (us) it takes to transmit 9 USB4 DP clock sync packets. */ #define DPIA_CLK_SYNC_DELAY … /* Extend interval between training status checks for manual testing. */ #define DPIA_DEBUG_EXTENDED_AUX_RD_INTERVAL_US … #define TRAINING_AUX_RD_INTERVAL … /* SET_CONFIG message types sent by driver. */ enum dpia_set_config_type { … }; /* Training stages (TS) in SET_CONFIG(SET_TRAINING) message. */ enum dpia_set_config_ts { … }; /* SET_CONFIG message data associated with messages sent by driver. */ dpia_set_config_data; /* Configure link as prescribed in link_setting; set LTTPR mode; and * Initialize link training settings. * Abort link training if sink unplug detected. * * @param link DPIA link being trained. * @param[in] link_setting Lane count, link rate and downspread control. * @param[out] lt_settings Link settings and drive settings (voltage swing and pre-emphasis). */ static enum link_training_result dpia_configure_link( struct dc_link *link, const struct link_resource *link_res, const struct dc_link_settings *link_setting, struct link_training_settings *lt_settings) { … } static enum dc_status core_link_send_set_config( struct dc_link *link, uint8_t msg_type, uint8_t msg_data) { … } /* Build SET_CONFIG message data payload for specified message type. */ static uint8_t dpia_build_set_config_data( enum dpia_set_config_type type, struct dc_link *link, struct link_training_settings *lt_settings) { … } /* Convert DC training pattern to DPIA training stage. */ static enum dc_status convert_trng_ptn_to_trng_stg(enum dc_dp_training_pattern tps, enum dpia_set_config_ts *ts) { … } /* Write training pattern to DPCD. */ static enum dc_status dpcd_set_lt_pattern( struct dc_link *link, enum dc_dp_training_pattern pattern, uint32_t hop) { … } /* Execute clock recovery phase of link training for specified hop in display * path.in non-transparent mode: * - Driver issues both DPCD and SET_CONFIG transactions. * - TPS1 is transmitted for any hops downstream of DPOA. * - Drive (VS/PE) only transmitted for the hop immediately downstream of DPOA. * - CR for the first hop (DPTX-to-DPIA) is assumed to be successful. * * @param link DPIA link being trained. * @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis). * @param hop Hop in display path. DPRX = 0. */ static enum link_training_result dpia_training_cr_non_transparent( struct dc_link *link, const struct link_resource *link_res, struct link_training_settings *lt_settings, uint32_t hop) { … } /* Execute clock recovery phase of link training in transparent LTTPR mode: * - Driver only issues DPCD transactions and leaves USB4 tunneling (SET_CONFIG) messages to DPIA. * - Driver writes TPS1 to DPCD to kick off training. * - Clock recovery (CR) for link is handled by DPOA, which reports result to DPIA on completion. * - DPIA communicates result to driver by updating CR status when driver reads DPCD. * * @param link DPIA link being trained. * @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis). */ static enum link_training_result dpia_training_cr_transparent( struct dc_link *link, const struct link_resource *link_res, struct link_training_settings *lt_settings) { … } /* Execute clock recovery phase of link training for specified hop in display * path. * * @param link DPIA link being trained. * @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis). * @param hop Hop in display path. DPRX = 0. */ static enum link_training_result dpia_training_cr_phase( struct dc_link *link, const struct link_resource *link_res, struct link_training_settings *lt_settings, uint32_t hop) { … } /* Return status read interval during equalization phase. */ static uint32_t dpia_get_eq_aux_rd_interval( const struct dc_link *link, const struct link_training_settings *lt_settings, uint32_t hop) { … } /* Execute equalization phase of link training for specified hop in display * path in non-transparent mode: * - driver issues both DPCD and SET_CONFIG transactions. * - TPSx is transmitted for any hops downstream of DPOA. * - Drive (VS/PE) only transmitted for the hop immediately downstream of DPOA. * - EQ for the first hop (DPTX-to-DPIA) is assumed to be successful. * - DPRX EQ only reported successful when both DPRX and DPIA requirements (clk sync packets sent) fulfilled. * * @param link DPIA link being trained. * @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis). * @param hop Hop in display path. DPRX = 0. */ static enum link_training_result dpia_training_eq_non_transparent( struct dc_link *link, const struct link_resource *link_res, struct link_training_settings *lt_settings, uint32_t hop) { … } /* Execute equalization phase of link training for specified hop in display * path in transparent LTTPR mode: * - driver only issues DPCD transactions leaves USB4 tunneling (SET_CONFIG) messages to DPIA. * - driver writes TPSx to DPCD to notify DPIA that is in equalization phase. * - equalization (EQ) for link is handled by DPOA, which reports result to DPIA on completion. * - DPIA communicates result to driver by updating EQ status when driver reads DPCD. * * @param link DPIA link being trained. * @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis). * @param hop Hop in display path. DPRX = 0. */ static enum link_training_result dpia_training_eq_transparent( struct dc_link *link, const struct link_resource *link_res, struct link_training_settings *lt_settings) { … } /* Execute equalization phase of link training for specified hop in display * path. * * @param link DPIA link being trained. * @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis). * @param hop Hop in display path. DPRX = 0. */ static enum link_training_result dpia_training_eq_phase( struct dc_link *link, const struct link_resource *link_res, struct link_training_settings *lt_settings, uint32_t hop) { … } /* End training of specified hop in display path. */ static enum dc_status dpcd_clear_lt_pattern( struct dc_link *link, uint32_t hop) { … } /* End training of specified hop in display path. * * In transparent LTTPR mode: * - driver clears training pattern for the specified hop in DPCD. * In non-transparent LTTPR mode: * - in addition to clearing training pattern, driver issues USB4 tunneling * (SET_CONFIG) messages to notify DPOA when training is done for first hop * (DPTX-to-DPIA) and last hop (DPRX). * * @param link DPIA link being trained. * @param hop Hop in display path. DPRX = 0. */ static enum link_training_result dpia_training_end( struct dc_link *link, struct link_training_settings *lt_settings, uint32_t hop) { … } /* When aborting training of specified hop in display path, clean up by: * - Attempting to clear DPCD TRAINING_PATTERN_SET, LINK_BW_SET and LANE_COUNT_SET. * - Sending SET_CONFIG(SET_LINK) with lane count and link rate set to 0. * * @param link DPIA link being trained. * @param hop Hop in display path. DPRX = 0. */ static void dpia_training_abort( struct dc_link *link, struct link_training_settings *lt_settings, uint32_t hop) { … } enum link_training_result dpia_perform_link_training( struct dc_link *link, const struct link_resource *link_res, const struct dc_link_settings *link_setting, bool skip_video_pattern) { … }
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