linux/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

/*
 * Copyright 2022 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

/* FILE POLICY AND INTENDED USAGE:
 * This file implements dp specific link capability retrieval sequence. It is
 * responsible for retrieving, parsing, overriding, deciding capability obtained
 * from dp link. Link capability consists of encoders, DPRXs, cables, retimers,
 * usb and all other possible backend capabilities. Other components should
 * include this header file in order to access link capability. Accessing link
 * capability by dereferencing dc_link outside dp_link_capability is not a
 * recommended method as it makes the component dependent on the underlying data
 * structure used to represent link capability instead of function interfaces.
 */

#include "link_dp_capability.h"
#include "link_ddc.h"
#include "link_dpcd.h"
#include "link_dp_dpia.h"
#include "link_dp_phy.h"
#include "link_edp_panel_control.h"
#include "link_dp_irq_handler.h"
#include "link/accessories/link_dp_trace.h"
#include "link/link_detection.h"
#include "link/link_validation.h"
#include "link_dp_training.h"
#include "atomfirmware.h"
#include "resource.h"
#include "link_enc_cfg.h"
#include "dc_dmub_srv.h"
#include "gpio_service_interface.h"

#define DC_LOGGER
#define DC_TRACE_LEVEL_MESSAGE(...)

#ifndef MAX
#define MAX
#endif
#ifndef MIN
#define MIN
#endif

struct dp_lt_fallback_entry {};

static const struct dp_lt_fallback_entry dp_lt_fallbacks[] =;

static const struct dc_link_settings fail_safe_link_settings =;

bool is_dp_active_dongle(const struct dc_link *link)
{}

bool is_dp_branch_device(const struct dc_link *link)
{}

static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
{}

uint8_t dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count)
{}

uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw)
{}

static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
{}

static union dp_cable_id intersect_cable_id(
		union dp_cable_id *a, union dp_cable_id *b)
{}

/*
 * Return PCON's post FRL link training supported BW if its non-zero, otherwise return max_supported_frl_bw.
 */
static uint32_t intersect_frl_link_bw_support(
	const uint32_t max_supported_frl_bw_in_kbps,
	const union hdmi_encoded_link_bw hdmi_encoded_link_bw)
{}

static enum clock_source_id get_clock_source_id(struct dc_link *link)
{}

static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
		int length)
{}

bool dp_is_fec_supported(const struct dc_link *link)
{}

bool dp_should_enable_fec(const struct dc_link *link)
{}

bool dp_is_128b_132b_signal(struct pipe_ctx *pipe_ctx)
{}

bool dp_is_lttpr_present(struct dc_link *link)
{}

/* in DP compliance test, DPR-120 may have
 * a random value in its MAX_LINK_BW dpcd field.
 * We map it to the maximum supported link rate that
 * is smaller than MAX_LINK_BW in this case.
 */
static enum dc_link_rate get_link_rate_from_max_link_bw(
		 uint8_t max_link_bw)
{}

static enum dc_link_rate get_lttpr_max_link_rate(struct dc_link *link)
{}

static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link)
{}

static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
{}

static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
{}

static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
{}

static enum dc_link_rate reduce_link_rate(const struct dc_link *link, enum dc_link_rate link_rate)
{}

static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
{}

static enum dc_link_rate increase_link_rate(struct dc_link *link,
		enum dc_link_rate link_rate)
{}

static bool decide_fallback_link_setting_max_bw_policy(
		struct dc_link *link,
		const struct dc_link_settings *max,
		struct dc_link_settings *cur,
		enum link_training_result training_result)
{}

/*
 * function: set link rate and lane count fallback based
 * on current link setting and last link training result
 * return value:
 *			true - link setting could be set
 *			false - has reached minimum setting
 *					and no further fallback could be done
 */
bool decide_fallback_link_setting(
		struct dc_link *link,
		struct dc_link_settings *max,
		struct dc_link_settings *cur,
		enum link_training_result training_result)
{}
static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
{}

bool edp_decide_link_settings(struct dc_link *link,
		struct dc_link_settings *link_setting, uint32_t req_bw)
{}

bool decide_edp_link_settings_with_dsc(struct dc_link *link,
		struct dc_link_settings *link_setting,
		uint32_t req_bw,
		enum dc_link_rate max_link_rate)
{}

static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
{}

bool link_decide_link_settings(struct dc_stream_state *stream,
	struct dc_link_settings *link_setting)
{}

enum dp_link_encoding link_dp_get_encoding_format(const struct dc_link_settings *link_settings)
{}

enum dp_link_encoding mst_decide_link_encoding_format(const struct dc_link *link)
{}

static void read_dp_device_vendor_id(struct dc_link *link)
{}

static enum dc_status wake_up_aux_channel(struct dc_link *link)
{}

static void get_active_converter_info(
	uint8_t data, struct dc_link *link)
{}

static void apply_usbc_combo_phy_reset_wa(struct dc_link *link,
		struct dc_link_settings *link_settings)
{}

bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
{}

void dpcd_set_source_specific_data(struct dc_link *link)
{}

void dpcd_write_cable_id_to_dprx(struct dc_link *link)
{}

static bool get_usbc_cable_id(struct dc_link *link, union dp_cable_id *cable_id)
{}

static void retrieve_cable_id(struct dc_link *link)
{}

bool read_is_mst_supported(struct dc_link *link)
{}

/* Read additional sink caps defined in source specific DPCD area
 * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
 * TODO: Add FS caps and read from DP_SOURCE_SINK_FS_CAP as well
 */
static bool dpcd_read_sink_ext_caps(struct dc_link *link)
{}

enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link)
{}

static bool retrieve_link_cap(struct dc_link *link)
{}

bool detect_dp_sink_caps(struct dc_link *link)
{}

void detect_edp_sink_caps(struct dc_link *link)
{}

bool dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
{}

const struct dc_link_settings *dp_get_verified_link_cap(
		const struct dc_link *link)
{}

struct dc_link_settings dp_get_max_link_cap(struct dc_link *link)
{}

static bool dp_verify_link_cap(
	struct dc_link *link,
	struct dc_link_settings *known_limit_link_setting,
	int *fail_count)
{}

bool dp_verify_link_cap_with_retries(
	struct dc_link *link,
	struct dc_link_settings *known_limit_link_setting,
	int attempts)
{}

/*
 * Check if there is a native DP or passive DP-HDMI dongle connected
 */
bool dp_is_sink_present(struct dc_link *link)
{}