linux/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

/*
 * Copyright 2022 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

/* FILE POLICY AND INTENDED USAGE:
 * This file implements retrieval and configuration of eDP panel features such
 * as PSR and ABM and it also manages specs defined eDP panel power sequences.
 */

#include "link_edp_panel_control.h"
#include "link_dpcd.h"
#include "link_dp_capability.h"
#include "dm_helpers.h"
#include "dal_asic_id.h"
#include "link_dp_phy.h"
#include "dce/dmub_psr.h"
#include "dc/dc_dmub_srv.h"
#include "dce/dmub_replay.h"
#include "abm.h"
#include "resource.h"
#define DC_LOGGER …
#define DC_LOGGER_INIT(logger) …

#define DP_SINK_PR_ENABLE_AND_CONFIGURATION …

/* Travis */
static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = …;
/* Nutmeg */
static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = …;

void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
{ … }

enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
{ … }

bool edp_set_backlight_level_nits(struct dc_link *link,
		bool isHDR,
		uint32_t backlight_millinits,
		uint32_t transition_time_in_ms)
{ … }

bool edp_get_backlight_level_nits(struct dc_link *link,
		uint32_t *backlight_millinits_avg,
		uint32_t *backlight_millinits_peak)
{ … }

bool edp_backlight_enable_aux(struct dc_link *link, bool enable)
{ … }

// we read default from 0x320 because we expect BIOS wrote it there
// regular get_backlight_nit reads from panel set at 0x326
static bool read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
{ … }

bool set_default_brightness_aux(struct dc_link *link)
{ … }

bool edp_is_ilr_optimization_enabled(struct dc_link *link)
{ … }

enum dc_link_rate get_max_link_rate_from_ilr_table(struct dc_link *link)
{ … }

bool edp_is_ilr_optimization_required(struct dc_link *link,
		struct dc_crtc_timing *crtc_timing)
{ … }

void edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd)
{ … }

void edp_set_panel_power(struct dc_link *link, bool powerOn)
{ … }

bool edp_wait_for_t12(struct dc_link *link)
{ … }

void edp_add_delay_for_T9(struct dc_link *link)
{ … }

bool edp_receiver_ready_T9(struct dc_link *link)
{ … }

bool edp_receiver_ready_T7(struct dc_link *link)
{ … }

bool edp_power_alpm_dpcd_enable(struct dc_link *link, bool enable)
{ … }

static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
{ … }

bool edp_set_backlight_level(const struct dc_link *link,
		uint32_t backlight_pwm_u16_16,
		uint32_t frame_ramp)
{ … }

bool edp_set_psr_allow_active(struct dc_link *link, const bool *allow_active,
		bool wait, bool force_static, const unsigned int *power_opts)
{ … }

bool edp_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
{ … }

static inline enum physical_phy_id
transmitter_to_phy_id(struct dc_link *link)
{ … }

bool edp_setup_psr(struct dc_link *link,
		const struct dc_stream_state *stream, struct psr_config *psr_config,
		struct psr_context *psr_context)
{ … }

void edp_get_psr_residency(const struct dc_link *link, uint32_t *residency, enum psr_residency_mode mode)
{ … }
bool edp_set_sink_vtotal_in_psr_active(const struct dc_link *link, uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
{ … }

bool edp_set_replay_allow_active(struct dc_link *link, const bool *allow_active,
	bool wait, bool force_static, const unsigned int *power_opts)
{ … }

bool edp_get_replay_state(const struct dc_link *link, uint64_t *state)
{ … }

bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream)
{ … }

/*
 * This is general Interface for Replay to set an 32 bit variable to dmub
 * replay_FW_Message_type: Indicates which instruction or variable pass to DMUB
 * cmd_data: Value of the config.
 */
bool edp_send_replay_cmd(struct dc_link *link,
			enum replay_FW_Message_type msg,
			union dmub_replay_cmd_set *cmd_data)
{ … }

bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal)
{ … }

bool edp_replay_residency(const struct dc_link *link,
	unsigned int *residency, const bool is_start, const enum pr_residency_mode mode)
{ … }

bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link,
	const unsigned int *power_opts, uint32_t coasting_vtotal)
{ … }

static struct abm *get_abm_from_stream_res(const struct dc_link *link)
{ … }

int edp_get_backlight_level(const struct dc_link *link)
{ … }

int edp_get_target_backlight_pwm(const struct dc_link *link)
{ … }

static void edp_set_assr_enable(const struct dc *pDC, struct dc_link *link,
		struct link_resource *link_res, bool enable)
{ … }

void edp_set_panel_assr(struct dc_link *link, struct pipe_ctx *pipe_ctx,
		enum dp_panel_mode *panel_mode, bool enable)
{ … }