/* * Copyright 2016 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #include "dm_services.h" #include "dc.h" #include "dcn10/dcn10_init.h" #include "resource.h" #include "include/irq_service_interface.h" #include "dcn10/dcn10_resource.h" #include "dcn10/dcn10_ipp.h" #include "dcn10/dcn10_mpc.h" #include "dcn10/dcn10_dwb.h" #include "irq/dcn10/irq_service_dcn10.h" #include "dcn10/dcn10_dpp.h" #include "dcn10/dcn10_optc.h" #include "dcn10/dcn10_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn10/dcn10_opp.h" #include "dcn10/dcn10_link_encoder.h" #include "dcn10/dcn10_stream_encoder.h" #include "dce/dce_clock_source.h" #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dce112/dce112_resource.h" #include "dcn10/dcn10_hubp.h" #include "dcn10/dcn10_hubbub.h" #include "dce/dce_panel_cntl.h" #include "soc15_hw_ip.h" #include "vega10_ip_offset.h" #include "dcn/dcn_1_0_offset.h" #include "dcn/dcn_1_0_sh_mask.h" #include "nbio/nbio_7_0_offset.h" #include "mmhub/mmhub_9_1_offset.h" #include "mmhub/mmhub_9_1_sh_mask.h" #include "reg_helper.h" #include "dce/dce_abm.h" #include "dce/dce_dmcu.h" #include "dce/dce_aux.h" #include "dce/dce_i2c.h" #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL #define mmDP0_DP_DPHY_INTERNAL_CTRL … #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX … #define mmDP1_DP_DPHY_INTERNAL_CTRL … #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX … #define mmDP2_DP_DPHY_INTERNAL_CTRL … #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX … #define mmDP3_DP_DPHY_INTERNAL_CTRL … #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX … #define mmDP4_DP_DPHY_INTERNAL_CTRL … #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX … #define mmDP5_DP_DPHY_INTERNAL_CTRL … #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX … #define mmDP6_DP_DPHY_INTERNAL_CTRL … #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX … #endif enum dcn10_clk_src_array_id { … }; /* begin ********************* * macros to expend register list macro defined in HW object header file */ /* DCN */ #define BASE_INNER(seg) … #define BASE(seg) … #define SR(reg_name) … #define SRI(reg_name, block, id) … #define SRII(reg_name, block, id) … #define VUPDATE_SRII(reg_name, block, id) … /* set field/register/bitfield name */ #define SFRB(field_name, reg_name, bitfield, post_fix) … /* NBIO */ #define NBIO_BASE_INNER(seg) … #define NBIO_BASE(seg) … #define NBIO_SR(reg_name) … /* MMHUB */ #define MMHUB_BASE_INNER(seg) … #define MMHUB_BASE(seg) … #define MMHUB_SR(reg_name) … /* macros to expend register list macro defined in HW object header file * end *********************/ static const struct dce_dmcu_registers dmcu_regs = …; static const struct dce_dmcu_shift dmcu_shift = …; static const struct dce_dmcu_mask dmcu_mask = …; static const struct dce_abm_registers abm_regs = …; static const struct dce_abm_shift abm_shift = …; static const struct dce_abm_mask abm_mask = …; #define stream_enc_regs(id) … static const struct dcn10_stream_enc_registers stream_enc_regs[] = …; static const struct dcn10_stream_encoder_shift se_shift = …; static const struct dcn10_stream_encoder_mask se_mask = …; #define audio_regs(id) … static const struct dce_audio_registers audio_regs[] = …; #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh) … static const struct dce_audio_shift audio_shift = …; static const struct dce_audio_mask audio_mask = …; #define aux_regs(id) … static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = …; #define hpd_regs(id) … static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = …; #define link_regs(id) … static const struct dcn10_link_enc_registers link_enc_regs[] = …; static const struct dcn10_link_enc_shift le_shift = …; static const struct dcn10_link_enc_mask le_mask = …; static const struct dce_panel_cntl_registers panel_cntl_regs[] = …; static const struct dce_panel_cntl_shift panel_cntl_shift = …; static const struct dce_panel_cntl_mask panel_cntl_mask = …; static const struct dce110_aux_registers_shift aux_shift = …; static const struct dce110_aux_registers_mask aux_mask = …; #define ipp_regs(id) … static const struct dcn10_ipp_registers ipp_regs[] = …; static const struct dcn10_ipp_shift ipp_shift = …; static const struct dcn10_ipp_mask ipp_mask = …; #define opp_regs(id) … static const struct dcn10_opp_registers opp_regs[] = …; static const struct dcn10_opp_shift opp_shift = …; static const struct dcn10_opp_mask opp_mask = …; #define aux_engine_regs(id) … static const struct dce110_aux_registers aux_engine_regs[] = …; #define tf_regs(id) … static const struct dcn_dpp_registers tf_regs[] = …; static const struct dcn_dpp_shift tf_shift = …; static const struct dcn_dpp_mask tf_mask = …; static const struct dcn_mpc_registers mpc_regs = …; static const struct dcn_mpc_shift mpc_shift = …; static const struct dcn_mpc_mask mpc_mask = …; #define tg_regs(id) … static const struct dcn_optc_registers tg_regs[] = …; static const struct dcn_optc_shift tg_shift = …; static const struct dcn_optc_mask tg_mask = …; static const struct bios_registers bios_regs = …; #define hubp_regs(id) … static const struct dcn_mi_registers hubp_regs[] = …; static const struct dcn_mi_shift hubp_shift = …; static const struct dcn_mi_mask hubp_mask = …; static const struct dcn_hubbub_registers hubbub_reg = …; static const struct dcn_hubbub_shift hubbub_shift = …; static const struct dcn_hubbub_mask hubbub_mask = …; static int map_transmitter_id_to_phy_instance( enum transmitter transmitter) { … } #define clk_src_regs(index, pllid) … static const struct dce110_clk_src_regs clk_src_regs[] = …; static const struct dce110_clk_src_shift cs_shift = …; static const struct dce110_clk_src_mask cs_mask = …; static const struct resource_caps res_cap = …; static const struct resource_caps rv2_res_cap = …; static const struct dc_plane_cap plane_cap = …; static const struct dc_debug_options debug_defaults_drv = …; static const struct dc_debug_options debug_defaults_diags = …; static void dcn10_dpp_destroy(struct dpp **dpp) { … } static struct dpp *dcn10_dpp_create( struct dc_context *ctx, uint32_t inst) { … } static struct input_pixel_processor *dcn10_ipp_create( struct dc_context *ctx, uint32_t inst) { … } static struct output_pixel_processor *dcn10_opp_create( struct dc_context *ctx, uint32_t inst) { … } static struct dce_aux *dcn10_aux_engine_create(struct dc_context *ctx, uint32_t inst) { … } #define i2c_inst_regs(id) … static const struct dce_i2c_registers i2c_hw_regs[] = …; static const struct dce_i2c_shift i2c_shifts = …; static const struct dce_i2c_mask i2c_masks = …; static struct dce_i2c_hw *dcn10_i2c_hw_create(struct dc_context *ctx, uint32_t inst) { … } static struct mpc *dcn10_mpc_create(struct dc_context *ctx) { … } static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx) { … } static struct timing_generator *dcn10_timing_generator_create( struct dc_context *ctx, uint32_t instance) { … } static const struct encoder_feature_support link_enc_feature = …; static struct link_encoder *dcn10_link_encoder_create( struct dc_context *ctx, const struct encoder_init_data *enc_init_data) { … } static struct panel_cntl *dcn10_panel_cntl_create(const struct panel_cntl_init_data *init_data) { … } static struct clock_source *dcn10_clock_source_create( struct dc_context *ctx, struct dc_bios *bios, enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) { … } static void read_dce_straps( struct dc_context *ctx, struct resource_straps *straps) { … } static struct audio *create_audio( struct dc_context *ctx, unsigned int inst) { … } static struct stream_encoder *dcn10_stream_encoder_create( enum engine_id eng_id, struct dc_context *ctx) { … } static const struct dce_hwseq_registers hwseq_reg = …; static const struct dce_hwseq_shift hwseq_shift = …; static const struct dce_hwseq_mask hwseq_mask = …; static struct dce_hwseq *dcn10_hwseq_create( struct dc_context *ctx) { … } static const struct resource_create_funcs res_create_funcs = …; static void dcn10_clock_source_destroy(struct clock_source **clk_src) { … } static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx) { … } static void dcn10_resource_destruct(struct dcn10_resource_pool *pool) { … } static struct hubp *dcn10_hubp_create( struct dc_context *ctx, uint32_t inst) { … } static void get_pixel_clock_parameters( const struct pipe_ctx *pipe_ctx, struct pixel_clk_params *pixel_clk_params) { … } static void build_clamping_params(struct dc_stream_state *stream) { … } static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx) { … } static enum dc_status build_mapped_resource( const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream) { … } static enum dc_status dcn10_add_stream_to_ctx( struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) { … } static struct pipe_ctx *dcn10_acquire_free_pipe_for_layer( const struct dc_state *cur_ctx, struct dc_state *new_ctx, const struct resource_pool *pool, const struct pipe_ctx *opp_head_pipe) { … } static bool dcn10_get_dcc_compression_cap(const struct dc *dc, const struct dc_dcc_surface_param *input, struct dc_surface_dcc_cap *output) { … } static void dcn10_destroy_resource_pool(struct resource_pool **pool) { … } static bool dcn10_validate_bandwidth( struct dc *dc, struct dc_state *context, bool fast_validate) { … } static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) { … } static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context) { … } static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *plane_state) { … } struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link( struct resource_context *res_ctx, const struct resource_pool *pool, struct dc_stream_state *stream) { … } static const struct dc_cap_funcs cap_funcs = …; static const struct resource_funcs dcn10_res_pool_funcs = …; static uint32_t read_pipe_fuses(struct dc_context *ctx) { … } static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks) { … } static bool dcn10_resource_construct( uint8_t num_virtual_links, struct dc *dc, struct dcn10_resource_pool *pool) { … } struct resource_pool *dcn10_create_resource_pool( const struct dc_init_data *init_data, struct dc *dc) { … }
Codebase Browser
linux