dcn30_optc.h | Explore in Territory

/*
 * Copyright 2020 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef __DC_OPTC_DCN30_H__
#define __DC_OPTC_DCN30_H__

#include "dcn20/dcn20_optc.h"

#define V_TOTAL_REGS_DCN30_SRI(inst) …

#define OPTC_COMMON_REG_LIST_DCN3_BASE(inst) …


#define OPTC_COMMON_REG_LIST_DCN3_0(inst) …

#define DCN30_VTOTAL_REGS_SF(mask_sh) …

#define OPTC_COMMON_MASK_SH_LIST_DCN3_BASE(mask_sh) …

#define OPTC_COMMON_MASK_SH_LIST_DCN3_0(mask_sh) …

#define OPTC_COMMON_MASK_SH_LIST_DCN30(mask_sh) …

void dcn30_timing_generator_init(struct optc *optc1);

void optc3_set_out_mux(struct timing_generator *optc, enum otg_out_mux_dest dest);

void optc3_lock(struct timing_generator *optc);

void optc3_lock_doublebuffer_enable(struct timing_generator *optc);

void optc3_lock_doublebuffer_disable(struct timing_generator *optc);

void optc3_set_drr_trigger_window(struct timing_generator *optc,
		uint32_t window_start, uint32_t window_end);

void optc3_triplebuffer_lock(struct timing_generator *optc);

void optc3_program_blank_color(struct timing_generator *optc,
		const struct tg_color *blank_color);

void optc3_set_vtotal_change_limit(struct timing_generator *optc,
		uint32_t limit);

void optc3_set_dsc_config(struct timing_generator *optc,
		enum optc_dsc_mode dsc_mode,
		uint32_t dsc_bytes_per_pixel,
		uint32_t dsc_slice_width);

void optc3_set_timing_db_mode(struct timing_generator *optc, bool enable);

void optc3_set_odm_bypass(struct timing_generator *optc,
		const struct dc_crtc_timing *dc_crtc_timing);
void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
		int segment_width, int last_segment_width);
void optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator *optc);
void optc3_tg_init(struct timing_generator *optc);
void optc3_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max);
#endif /* __DC_OPTC_DCN30_H__ */
linux/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
