/* * Copyright (C) 2021 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _dpcs_2_0_3_OFFSET_HEADER #define _dpcs_2_0_3_OFFSET_HEADER // addressBlock: dpcssysa_dpcs0_dpcstx0_dispdec // base address: 0x0 #define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL … #define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX … #define mmDPCSTX0_DPCSTX_TX_CNTL … #define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX … #define mmDPCSTX0_DPCSTX_CBUS_CNTL … #define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX … #define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL … #define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX … #define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR … #define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX … #define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA … #define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX … // addressBlock: dpcssysa_dpcs0_rdpcstx0_dispdec // base address: 0x0 #define mmRDPCSTX0_RDPCSTX_CNTL … #define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX … #define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL … #define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX … #define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL … #define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX … #define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA … #define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX … #define mmRDPCSTX0_RDPCS_TX_CR_ADDR … #define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX … #define mmRDPCSTX0_RDPCS_TX_CR_DATA … #define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX … #define mmRDPCSTX0_RDPCSTX_SCRATCH … #define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL0 … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL1 … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL2 … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL3 … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL4 … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL5 … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL6 … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL7 … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL8 … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL9 … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL10 … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL11 … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL12 … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL13 … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL14 … #define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX … // addressBlock: dpcssysa_dpcs0_dpcstx1_dispdec // base address: 0x360 #define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL … #define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL_BASE_IDX … #define mmDPCSTX1_DPCSTX_TX_CNTL … #define mmDPCSTX1_DPCSTX_TX_CNTL_BASE_IDX … #define mmDPCSTX1_DPCSTX_CBUS_CNTL … #define mmDPCSTX1_DPCSTX_CBUS_CNTL_BASE_IDX … #define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL … #define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL_BASE_IDX … #define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR … #define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX … #define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA … #define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX … // addressBlock: dpcssysa_dpcs0_rdpcstx1_dispdec // base address: 0x360 #define mmRDPCSTX1_RDPCSTX_CNTL … #define mmRDPCSTX1_RDPCSTX_CNTL_BASE_IDX … #define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL … #define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX … #define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL … #define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX … #define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA … #define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX … #define mmRDPCSTX1_RDPCS_TX_CR_ADDR … #define mmRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX … #define mmRDPCSTX1_RDPCS_TX_CR_DATA … #define mmRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX … #define mmRDPCSTX1_RDPCSTX_SCRATCH … #define mmRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL0 … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL1 … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL2 … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL3 … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL4 … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL5 … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL6 … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL7 … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL8 … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL9 … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL10 … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL11 … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL12 … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL13 … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL14 … #define mmRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX … #endif
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