/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * * Bluetooth support for Intel PCIe devices * * Copyright (C) 2024 Intel Corporation */ /* Control and Status Register(BTINTEL_PCIE_CSR) */ #define BTINTEL_PCIE_CSR_BASE … #define BTINTEL_PCIE_CSR_FUNC_CTRL_REG … #define BTINTEL_PCIE_CSR_HW_REV_REG … #define BTINTEL_PCIE_CSR_RF_ID_REG … #define BTINTEL_PCIE_CSR_BOOT_STAGE_REG … #define BTINTEL_PCIE_CSR_CI_ADDR_LSB_REG … #define BTINTEL_PCIE_CSR_CI_ADDR_MSB_REG … #define BTINTEL_PCIE_CSR_IMG_RESPONSE_REG … #define BTINTEL_PCIE_CSR_HBUS_TARG_WRPTR … /* BTINTEL_PCIE_CSR Function Control Register */ #define BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_ENA … #define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_INIT … #define BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_INIT … #define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_STS … #define BTINTEL_PCIE_CSR_FUNC_CTRL_SW_RESET … /* Value for BTINTEL_PCIE_CSR_BOOT_STAGE register */ #define BTINTEL_PCIE_CSR_BOOT_STAGE_ROM … #define BTINTEL_PCIE_CSR_BOOT_STAGE_IML … #define BTINTEL_PCIE_CSR_BOOT_STAGE_OPFW … #define BTINTEL_PCIE_CSR_BOOT_STAGE_ROM_LOCKDOWN … #define BTINTEL_PCIE_CSR_BOOT_STAGE_IML_LOCKDOWN … #define BTINTEL_PCIE_CSR_BOOT_STAGE_MAC_ACCESS_ON … #define BTINTEL_PCIE_CSR_BOOT_STAGE_ALIVE … /* Registers for MSI-X */ #define BTINTEL_PCIE_CSR_MSIX_BASE … #define BTINTEL_PCIE_CSR_MSIX_FH_INT_CAUSES … #define BTINTEL_PCIE_CSR_MSIX_FH_INT_MASK … #define BTINTEL_PCIE_CSR_MSIX_HW_INT_CAUSES … #define BTINTEL_PCIE_CSR_MSIX_HW_INT_MASK … #define BTINTEL_PCIE_CSR_MSIX_AUTOMASK_ST … #define BTINTEL_PCIE_CSR_MSIX_AUTOMASK_EN … #define BTINTEL_PCIE_CSR_MSIX_IVAR_BASE … #define BTINTEL_PCIE_CSR_MSIX_IVAR(cause) … /* Causes for the FH register interrupts */ enum msix_fh_int_causes { … }; /* Causes for the HW register interrupts */ enum msix_hw_int_causes { … }; #define BTINTEL_PCIE_MSIX_NON_AUTO_CLEAR_CAUSE … /* Minimum and Maximum number of MSI-X Vector * Intel Bluetooth PCIe support only 1 vector */ #define BTINTEL_PCIE_MSIX_VEC_MAX … #define BTINTEL_PCIE_MSIX_VEC_MIN … /* Default poll time for MAC access during init */ #define BTINTEL_DEFAULT_MAC_ACCESS_TIMEOUT_US … /* Default interrupt timeout in msec */ #define BTINTEL_DEFAULT_INTR_TIMEOUT … /* The number of descriptors in TX/RX queues */ #define BTINTEL_DESCS_COUNT … /* Number of Queue for TX and RX * It indicates the index of the IA(Index Array) */ enum { … }; /* The size of DMA buffer for TX and RX in bytes */ #define BTINTEL_PCIE_BUFFER_SIZE … /* DMA allocation alignment */ #define BTINTEL_PCIE_DMA_POOL_ALIGNMENT … #define BTINTEL_PCIE_TX_WAIT_TIMEOUT_MS … /* Doorbell vector for TFD */ #define BTINTEL_PCIE_TX_DB_VEC … /* Number of pending RX requests for downlink */ #define BTINTEL_PCIE_RX_MAX_QUEUE … /* Doorbell vector for FRBD */ #define BTINTEL_PCIE_RX_DB_VEC … /* RBD buffer size mapping */ #define BTINTEL_PCIE_RBD_SIZE_4K … /* * Struct for Context Information (v2) * * All members are write-only for host and read-only for device. * * @version: Version of context information * @size: Size of context information * @config: Config with which host wants peripheral to execute * Subset of capability register published by device * @addr_tr_hia: Address of TR Head Index Array * @addr_tr_tia: Address of TR Tail Index Array * @addr_cr_hia: Address of CR Head Index Array * @addr_cr_tia: Address of CR Tail Index Array * @num_tr_ia: Number of entries in TR Index Arrays * @num_cr_ia: Number of entries in CR Index Arrays * @rbd_siz: RBD Size { 0x4=4K } * @addr_tfdq: Address of TFD Queue(tx) * @addr_urbdq0: Address of URBD Queue(tx) * @num_tfdq: Number of TFD in TFD Queue(tx) * @num_urbdq0: Number of URBD in URBD Queue(tx) * @tfdq_db_vec: Queue number of TFD * @urbdq0_db_vec: Queue number of URBD * @addr_frbdq: Address of FRBD Queue(rx) * @addr_urbdq1: Address of URBD Queue(rx) * @num_frbdq: Number of FRBD in FRBD Queue(rx) * @frbdq_db_vec: Queue number of FRBD * @num_urbdq1: Number of URBD in URBD Queue(rx) * @urbdq_db_vec: Queue number of URBDQ1 * @tr_msi_vec: Transfer Ring MSI-X Vector * @cr_msi_vec: Completion Ring MSI-X Vector * @dbgc_addr: DBGC first fragment address * @dbgc_size: DBGC buffer size * @early_enable: Enarly debug enable * @dbg_output_mode: Debug output mode * Bit[4] DBGC O/P { 0=SRAM, 1=DRAM(not relevant for NPK) } * Bit[5] DBGC I/P { 0=BDBG, 1=DBGI } * Bits[6:7] DBGI O/P(relevant if bit[5] = 1) * 0=BT DBGC, 1=WiFi DBGC, 2=NPK } * @dbg_preset: Debug preset * @ext_addr: Address of context information extension * @ext_size: Size of context information part * * Total 38 DWords */ struct ctx_info { … } __packed; /* Transfer Descriptor for TX * @type: Not in use. Set to 0x0 * @size: Size of data in the buffer * @addr: DMA Address of buffer */ struct tfd { … } __packed; /* URB Descriptor for TX * @tfd_index: Index of TFD in TFDQ + 1 * @num_txq: Queue index of TFD Queue * @cmpl_count: Completion count. Always 0x01 * @immediate_cmpl: Immediate completion flag: Always 0x01 */ struct urbd0 { … } __packed; /* FRB Descriptor for RX * @tag: RX buffer tag (index of RX buffer queue) * @addr: Address of buffer */ struct frbd { … } __packed; /* URB Descriptor for RX * @frbd_tag: Tag from FRBD * @status: Status */ struct urbd1 { … } __packed; /* RFH header in RX packet * @packet_len: Length of the data in the buffer * @rxq: RX Queue number * @cmd_id: Command ID. Not in Use */ struct rfh_hdr { … } __packed; /* Internal data buffer * @data: pointer to the data buffer * @p_addr: physical address of data buffer */ struct data_buf { … }; /* Index Array */ struct ia { … }; /* Structure for TX Queue * @count: Number of descriptors * @tfds: Array of TFD * @urbd0s: Array of URBD0 * @buf: Array of data_buf structure */ struct txq { … }; /* Structure for RX Queue * @count: Number of descriptors * @frbds: Array of FRBD * @urbd1s: Array of URBD1 * @buf: Array of data_buf structure */ struct rxq { … }; /* struct btintel_pcie_data * @pdev: pci device * @hdev: hdev device * @flags: driver state * @irq_lock: spinlock for MSI-X * @hci_rx_lock: spinlock for HCI RX flow * @base_addr: pci base address (from BAR) * @msix_entries: array of MSI-X entries * @msix_enabled: true if MSI-X is enabled; * @alloc_vecs: number of interrupt vectors allocated * @def_irq: default irq for all causes * @fh_init_mask: initial unmasked rxq causes * @hw_init_mask: initial unmaksed hw causes * @boot_stage_cache: cached value of boot stage register * @img_resp_cache: cached value of image response register * @cnvi: CNVi register value * @cnvr: CNVr register value * @gp0_received: condition for gp0 interrupt * @gp0_wait_q: wait_q for gp0 interrupt * @tx_wait_done: condition for tx interrupt * @tx_wait_q: wait_q for tx interrupt * @workqueue: workqueue for RX work * @rx_skb_q: SKB queue for RX packet * @rx_work: RX work struct to process the RX packet in @rx_skb_q * @dma_pool: DMA pool for descriptors, index array and ci * @dma_p_addr: DMA address for pool * @dma_v_addr: address of pool * @ci_p_addr: DMA address for CI struct * @ci: CI struct * @ia: Index Array struct * @txq: TX Queue struct * @rxq: RX Queue struct */ struct btintel_pcie_data { … }; static inline u32 btintel_pcie_rd_reg32(struct btintel_pcie_data *data, u32 offset) { … } static inline void btintel_pcie_wr_reg8(struct btintel_pcie_data *data, u32 offset, u8 val) { … } static inline void btintel_pcie_wr_reg32(struct btintel_pcie_data *data, u32 offset, u32 val) { … } static inline void btintel_pcie_set_reg_bits(struct btintel_pcie_data *data, u32 offset, u32 bits) { … } static inline void btintel_pcie_clr_reg_bits(struct btintel_pcie_data *data, u32 offset, u32 bits) { … }
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