/* * Copyright 2019 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #ifndef __DAL_DCN31_HPO_DP_STREAM_ENCODER_H__ #define __DAL_DCN31_HPO_DP_STREAM_ENCODER_H__ #include "dcn30/dcn30_vpg.h" #include "dcn31/dcn31_apg.h" #include "stream_encoder.h" #define DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(hpo_dp_stream_encoder) … /* Define MSA_DATA_LANE_[0-3] fields to make programming easier */ #define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_0__SHIFT … #define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_1__SHIFT … #define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_2__SHIFT … #define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_3__SHIFT … #define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_0_MASK … #define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_1_MASK … #define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_2_MASK … #define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_3_MASK … #define DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id) … #define DCN3_1_HPO_DP_STREAM_ENC_REGS … #define DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(mask_sh) … #define DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(type) … struct dcn31_hpo_dp_stream_encoder_registers { … }; struct dcn31_hpo_dp_stream_encoder_shift { … }; struct dcn31_hpo_dp_stream_encoder_mask { … }; struct dcn31_hpo_dp_stream_encoder { … }; void dcn31_hpo_dp_stream_encoder_construct( struct dcn31_hpo_dp_stream_encoder *enc3, struct dc_context *ctx, struct dc_bios *bp, uint32_t inst, enum engine_id eng_id, struct vpg *vpg, struct apg *apg, const struct dcn31_hpo_dp_stream_encoder_registers *regs, const struct dcn31_hpo_dp_stream_encoder_shift *hpo_se_shift, const struct dcn31_hpo_dp_stream_encoder_mask *hpo_se_mask); #endif // __DAL_DCN31_HPO_STREAM_ENCODER_H__
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