/* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright (C) 2013--2024 Intel Corporation */ #ifndef IPU6_ISYS_H #define IPU6_ISYS_H #include <linux/irqreturn.h> #include <linux/list.h> #include <linux/mutex.h> #include <linux/pm_qos.h> #include <linux/spinlock_types.h> #include <linux/types.h> #include <media/media-device.h> #include <media/v4l2-async.h> #include <media/v4l2-device.h> #include "ipu6.h" #include "ipu6-fw-isys.h" #include "ipu6-isys-csi2.h" #include "ipu6-isys-video.h" struct ipu6_bus_device; #define IPU6_ISYS_ENTITY_PREFIX … /* FW support max 16 streams */ #define IPU6_ISYS_MAX_STREAMS … #define ISYS_UNISPART_IRQS … #define IPU6_ISYS_2600_MEM_LINE_ALIGN … /* * Current message queue configuration. These must be big enough * so that they never gets full. Queues are located in system memory */ #define IPU6_ISYS_SIZE_RECV_QUEUE … #define IPU6_ISYS_SIZE_SEND_QUEUE … #define IPU6_ISYS_SIZE_PROXY_RECV_QUEUE … #define IPU6_ISYS_SIZE_PROXY_SEND_QUEUE … #define IPU6_ISYS_NUM_RECV_QUEUE … #define IPU6_ISYS_MIN_WIDTH … #define IPU6_ISYS_MIN_HEIGHT … #define IPU6_ISYS_MAX_WIDTH … #define IPU6_ISYS_MAX_HEIGHT … /* the threshold granularity is 2KB on IPU6 */ #define IPU6_SRAM_GRANULARITY_SHIFT … #define IPU6_SRAM_GRANULARITY_SIZE … /* the threshold granularity is 1KB on IPU6SE */ #define IPU6SE_SRAM_GRANULARITY_SHIFT … #define IPU6SE_SRAM_GRANULARITY_SIZE … /* IS pixel buffer is 256KB, MaxSRAMSize is 200KB on IPU6 */ #define IPU6_MAX_SRAM_SIZE … /* IS pixel buffer is 128KB, MaxSRAMSize is 96KB on IPU6SE */ #define IPU6SE_MAX_SRAM_SIZE … #define IPU6EP_LTR_VALUE … #define IPU6EP_MIN_MEMOPEN_TH … #define IPU6EP_MTL_LTR_VALUE … #define IPU6EP_MTL_MIN_MEMOPEN_TH … struct ltr_did { … }; struct isys_iwake_watermark { … }; struct ipu6_isys_csi2_config { … }; struct sensor_async_sd { … }; /* * struct ipu6_isys * * @media_dev: Media device * @v4l2_dev: V4L2 device * @adev: ISYS bus device * @power: Is ISYS powered on or not? * @isr_bits: Which bits does the ISR handle? * @power_lock: Serialise access to power (power state in general) * @csi2_rx_ctrl_cached: cached shared value between all CSI2 receivers * @streams_lock: serialise access to streams * @streams: streams per firmware stream ID * @fwcom: fw communication layer private pointer * or optional external library private pointer * @line_align: line alignment in memory * @phy_termcal_val: the termination calibration value, only used for DWC PHY * @need_reset: Isys requires d0i0->i3 transition * @ref_count: total number of callers fw open * @mutex: serialise access isys video open/release related operations * @stream_mutex: serialise stream start and stop, queueing requests * @pdata: platform data pointer * @csi2: CSI-2 receivers */ struct ipu6_isys { … }; struct isys_fw_msgs { … }; struct isys_fw_msgs *ipu6_get_fw_msg_buf(struct ipu6_isys_stream *stream); void ipu6_put_fw_msg_buf(struct ipu6_isys *isys, u64 data); void ipu6_cleanup_fw_msg_bufs(struct ipu6_isys *isys); extern const struct v4l2_ioctl_ops ipu6_isys_ioctl_ops; void isys_setup_hw(struct ipu6_isys *isys); irqreturn_t isys_isr(struct ipu6_bus_device *adev); void update_watermark_setting(struct ipu6_isys *isys); int ipu6_isys_mcd_phy_set_power(struct ipu6_isys *isys, struct ipu6_isys_csi2_config *cfg, const struct ipu6_isys_csi2_timing *timing, bool on); int ipu6_isys_dwc_phy_set_power(struct ipu6_isys *isys, struct ipu6_isys_csi2_config *cfg, const struct ipu6_isys_csi2_timing *timing, bool on); int ipu6_isys_jsl_phy_set_power(struct ipu6_isys *isys, struct ipu6_isys_csi2_config *cfg, const struct ipu6_isys_csi2_timing *timing, bool on); #endif /* IPU6_ISYS_H */
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