/* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright (C) 2023--2024 Intel Corporation */ #ifndef IPU6_PLATFORM_BUTTRESS_REGS_H #define IPU6_PLATFORM_BUTTRESS_REGS_H #include <linux/bits.h> /* IS_WORKPOINT_REQ */ #define IPU6_BUTTRESS_REG_IS_FREQ_CTL … /* PS_WORKPOINT_REQ */ #define IPU6_BUTTRESS_REG_PS_FREQ_CTL … /* should be tuned for real silicon */ #define IPU6_IS_FREQ_CTL_DEFAULT_RATIO … #define IPU6SE_IS_FREQ_CTL_DEFAULT_RATIO … #define IPU6_PS_FREQ_CTL_DEFAULT_RATIO … #define IPU6_IS_FREQ_CTL_DEFAULT_QOS_FLOOR_RATIO … #define IPU6_PS_FREQ_CTL_DEFAULT_QOS_FLOOR_RATIO … #define IPU6_BUTTRESS_PWR_STATE_IS_PWR_SHIFT … #define IPU6_BUTTRESS_PWR_STATE_IS_PWR_MASK … #define IPU6_BUTTRESS_PWR_STATE_PS_PWR_SHIFT … #define IPU6_BUTTRESS_PWR_STATE_PS_PWR_MASK … #define IPU6_BUTTRESS_PWR_STATE_DN_DONE … #define IPU6_BUTTRESS_PWR_STATE_UP_PROCESS … #define IPU6_BUTTRESS_PWR_STATE_DN_PROCESS … #define IPU6_BUTTRESS_PWR_STATE_UP_DONE … #define IPU6_BUTTRESS_REG_FPGA_SUPPORT_0 … #define IPU6_BUTTRESS_REG_FPGA_SUPPORT_1 … #define IPU6_BUTTRESS_REG_FPGA_SUPPORT_2 … #define IPU6_BUTTRESS_REG_FPGA_SUPPORT_3 … #define IPU6_BUTTRESS_REG_FPGA_SUPPORT_4 … #define IPU6_BUTTRESS_REG_FPGA_SUPPORT_5 … #define IPU6_BUTTRESS_REG_FPGA_SUPPORT_6 … #define IPU6_BUTTRESS_REG_FPGA_SUPPORT_7 … #define BUTTRESS_REG_WDT … #define BUTTRESS_REG_BTRS_CTRL … #define BUTTRESS_REG_BTRS_CTRL_STALL_MODE_VC0 … #define BUTTRESS_REG_BTRS_CTRL_STALL_MODE_VC1 … #define BUTTRESS_REG_BTRS_CTRL_REF_CLK_IND … #define BUTTRESS_REG_FW_RESET_CTL … #define BUTTRESS_FW_RESET_CTL_START … #define BUTTRESS_FW_RESET_CTL_DONE … #define BUTTRESS_REG_IS_FREQ_CTL … #define BUTTRESS_REG_PS_FREQ_CTL … #define BUTTRESS_FREQ_CTL_START … #define BUTTRESS_FREQ_CTL_ICCMAX_LEVEL … #define BUTTRESS_FREQ_CTL_QOS_FLOOR_MASK … #define BUTTRESS_FREQ_CTL_RATIO_MASK … #define BUTTRESS_REG_PWR_STATE … #define BUTTRESS_PWR_STATE_RESET … #define BUTTRESS_PWR_STATE_PWR_ON_DONE … #define BUTTRESS_PWR_STATE_PWR_RDY … #define BUTTRESS_PWR_STATE_PWR_IDLE … #define BUTTRESS_PWR_STATE_HH_STATUS_MASK … enum { … }; #define BUTTRESS_PWR_STATE_IS_PWR_FSM_MASK … #define BUTTRESS_PWR_STATE_IS_PWR_FSM_IDLE … #define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_PLL_CMP … #define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_CLKACK … #define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_PG_ACK … #define BUTTRESS_PWR_STATE_IS_PWR_FSM_RST_ASSRT_CYCLES … #define BUTTRESS_PWR_STATE_IS_PWR_FSM_STOP_CLK_CYCLES1 … #define BUTTRESS_PWR_STATE_IS_PWR_FSM_STOP_CLK_CYCLES2 … #define BUTTRESS_PWR_STATE_IS_PWR_FSM_RST_DEASSRT_CYCLES … #define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_FUSE_WR_CMP … #define BUTTRESS_PWR_STATE_IS_PWR_FSM_BRK_POINT … #define BUTTRESS_PWR_STATE_IS_PWR_FSM_IS_RDY … #define BUTTRESS_PWR_STATE_IS_PWR_FSM_HALT_HALTED … #define BUTTRESS_PWR_STATE_IS_PWR_FSM_RST_DURATION_CNT3 … #define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_CLKACK_PD … #define BUTTRESS_PWR_STATE_IS_PWR_FSM_PD_BRK_POINT … #define BUTTRESS_PWR_STATE_IS_PWR_FSM_WAIT_4_PD_PG_ACK0 … #define BUTTRESS_PWR_STATE_PS_PWR_FSM_MASK … #define BUTTRESS_PWR_STATE_PS_PWR_FSM_IDLE … #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_PU_PLL_IP_RDY … #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_RO_PRE_CNT_EXH … #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_PU_VGI_PWRGOOD … #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_RO_POST_CNT_EXH … #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WR_PLL_RATIO … #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_PU_PLL_CMP … #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_PU_CLKACK … #define BUTTRESS_PWR_STATE_PS_PWR_FSM_RST_ASSRT_CYCLES … #define BUTTRESS_PWR_STATE_PS_PWR_FSM_STOP_CLK_CYCLES1 … #define BUTTRESS_PWR_STATE_PS_PWR_FSM_STOP_CLK_CYCLES2 … #define BUTTRESS_PWR_STATE_PS_PWR_FSM_RST_DEASSRT_CYCLES … #define BUTTRESS_PWR_STATE_PS_PWR_FSM_PU_BRK_PNT … #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_FUSE_ACCPT … #define BUTTRESS_PWR_STATE_PS_PWR_FSM_PS_PWR_UP … #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_4_HALTED … #define BUTTRESS_PWR_STATE_PS_PWR_FSM_RESET_CNT3 … #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_PD_CLKACK … #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_PD_OFF_IND … #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_DVFS_PH4 … #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_DVFS_PLL_CMP … #define BUTTRESS_PWR_STATE_PS_PWR_FSM_WAIT_DVFS_CLKACK … #define BUTTRESS_REG_SECURITY_CTL … #define BUTTRESS_REG_SKU … #define BUTTRESS_REG_SECURITY_TOUCH … #define BUTTRESS_REG_CAMERA_MASK … #define BUTTRESS_SECURITY_CTL_FW_SECURE_MODE … #define BUTTRESS_SECURITY_CTL_FW_SETUP_MASK … #define BUTTRESS_SECURITY_CTL_FW_SETUP_DONE … #define BUTTRESS_SECURITY_CTL_AUTH_DONE … #define BUTTRESS_SECURITY_CTL_AUTH_FAILED … #define BUTTRESS_REG_FW_SOURCE_BASE_LO … #define BUTTRESS_REG_FW_SOURCE_BASE_HI … #define BUTTRESS_REG_FW_SOURCE_SIZE … #define BUTTRESS_REG_ISR_STATUS … #define BUTTRESS_REG_ISR_ENABLED_STATUS … #define BUTTRESS_REG_ISR_ENABLE … #define BUTTRESS_REG_ISR_CLEAR … #define BUTTRESS_ISR_IS_IRQ … #define BUTTRESS_ISR_PS_IRQ … #define BUTTRESS_ISR_IPC_EXEC_DONE_BY_CSE … #define BUTTRESS_ISR_IPC_EXEC_DONE_BY_ISH … #define BUTTRESS_ISR_IPC_FROM_CSE_IS_WAITING … #define BUTTRESS_ISR_IPC_FROM_ISH_IS_WAITING … #define BUTTRESS_ISR_CSE_CSR_SET … #define BUTTRESS_ISR_ISH_CSR_SET … #define BUTTRESS_ISR_SPURIOUS_CMP … #define BUTTRESS_ISR_WATCHDOG_EXPIRED … #define BUTTRESS_ISR_PUNIT_2_IUNIT_IRQ … #define BUTTRESS_ISR_SAI_VIOLATION … #define BUTTRESS_ISR_HW_ASSERTION … #define BUTTRESS_ISR_IS_CORRECTABLE_MEM_ERR … #define BUTTRESS_ISR_IS_FATAL_MEM_ERR … #define BUTTRESS_ISR_IS_NON_FATAL_MEM_ERR … #define BUTTRESS_ISR_PS_CORRECTABLE_MEM_ERR … #define BUTTRESS_ISR_PS_FATAL_MEM_ERR … #define BUTTRESS_ISR_PS_NON_FATAL_MEM_ERR … #define BUTTRESS_ISR_PS_FAST_THROTTLE … #define BUTTRESS_ISR_UFI_ERROR … #define BUTTRESS_REG_IU2CSEDB0 … #define BUTTRESS_IU2CSEDB0_BUSY … #define BUTTRESS_IU2CSEDB0_IPC_CLIENT_ID_VAL … #define BUTTRESS_REG_IU2CSEDATA0 … #define BUTTRESS_IU2CSEDATA0_IPC_BOOT_LOAD … #define BUTTRESS_IU2CSEDATA0_IPC_AUTH_RUN … #define BUTTRESS_IU2CSEDATA0_IPC_AUTH_REPLACE … #define BUTTRESS_IU2CSEDATA0_IPC_UPDATE_SECURE_TOUCH … #define BUTTRESS_CSE2IUDATA0_IPC_BOOT_LOAD_DONE … #define BUTTRESS_CSE2IUDATA0_IPC_AUTH_RUN_DONE … #define BUTTRESS_CSE2IUDATA0_IPC_AUTH_REPLACE_DONE … #define BUTTRESS_CSE2IUDATA0_IPC_UPDATE_SECURE_TOUCH_DONE … #define BUTTRESS_REG_IU2CSECSR … #define BUTTRESS_IU2CSECSR_IPC_PEER_COMP_ACTIONS_RST_PHASE1 … #define BUTTRESS_IU2CSECSR_IPC_PEER_COMP_ACTIONS_RST_PHASE2 … #define BUTTRESS_IU2CSECSR_IPC_PEER_QUERIED_IP_COMP_ACTIONS_RST_PHASE … #define BUTTRESS_IU2CSECSR_IPC_PEER_ASSERTED_REG_VALID_REQ … #define BUTTRESS_IU2CSECSR_IPC_PEER_ACKED_REG_VALID … #define BUTTRESS_IU2CSECSR_IPC_PEER_DEASSERTED_REG_VALID_REQ … #define BUTTRESS_REG_CSE2IUDB0 … #define BUTTRESS_REG_CSE2IUCSR … #define BUTTRESS_REG_CSE2IUDATA0 … /* 0x20 == NACK, 0xf == unknown command */ #define BUTTRESS_CSE2IUDATA0_IPC_NACK … #define BUTTRESS_CSE2IUDATA0_IPC_NACK_MASK … #define BUTTRESS_REG_ISH2IUCSR … #define BUTTRESS_REG_ISH2IUDB0 … #define BUTTRESS_REG_ISH2IUDATA0 … #define BUTTRESS_REG_IU2ISHDB0 … #define BUTTRESS_REG_IU2ISHDATA0 … #define BUTTRESS_REG_IU2ISHDATA1 … #define BUTTRESS_REG_IU2ISHCSR … #define BUTTRESS_REG_FABRIC_CMD … #define BUTTRESS_FABRIC_CMD_START_TSC_SYNC … #define BUTTRESS_FABRIC_CMD_IS_DRAIN … #define BUTTRESS_REG_TSW_CTL … #define BUTTRESS_TSW_CTL_SOFT_RESET … #define BUTTRESS_REG_TSC_LO … #define BUTTRESS_REG_TSC_HI … #define BUTTRESS_IRQS … #define BUTTRESS_EVENT … #endif /* IPU6_PLATFORM_BUTTRESS_REGS_H */
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