/* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright (C) 2018 - 2024 Intel Corporation */ #ifndef IPU6_PLATFORM_REGS_H #define IPU6_PLATFORM_REGS_H #include <linux/bits.h> /* * IPU6 uses uniform address within IPU6, therefore all subsystem registers * locates in one single space starts from 0 but in different sctions with * different addresses, the subsystem offsets are defined to 0 as the * register definition will have the address offset to 0. */ #define IPU6_UNIFIED_OFFSET … #define IPU6_ISYS_IOMMU0_OFFSET … #define IPU6_ISYS_IOMMU1_OFFSET … #define IPU6_ISYS_IOMMUI_OFFSET … #define IPU6_PSYS_IOMMU0_OFFSET … #define IPU6_PSYS_IOMMU1_OFFSET … #define IPU6_PSYS_IOMMU1R_OFFSET … #define IPU6_PSYS_IOMMUI_OFFSET … /* the offset from IOMMU base register */ #define IPU6_MMU_L1_STREAM_ID_REG_OFFSET … #define IPU6_MMU_L2_STREAM_ID_REG_OFFSET … #define IPU6_PSYS_MMU1W_L2_STREAM_ID_REG_OFFSET … #define IPU6_MMU_INFO_OFFSET … #define IPU6_ISYS_SPC_OFFSET … #define IPU6SE_PSYS_SPC_OFFSET … #define IPU6_PSYS_SPC_OFFSET … #define IPU6_ISYS_DMEM_OFFSET … #define IPU6_PSYS_DMEM_OFFSET … #define IPU6_REG_ISYS_UNISPART_IRQ_EDGE … #define IPU6_REG_ISYS_UNISPART_IRQ_MASK … #define IPU6_REG_ISYS_UNISPART_IRQ_STATUS … #define IPU6_REG_ISYS_UNISPART_IRQ_CLEAR … #define IPU6_REG_ISYS_UNISPART_IRQ_ENABLE … #define IPU6_REG_ISYS_UNISPART_IRQ_LEVEL_NOT_PULSE … #define IPU6_REG_ISYS_UNISPART_SW_IRQ_REG … #define IPU6_REG_ISYS_UNISPART_SW_IRQ_MUX_REG … #define IPU6_ISYS_UNISPART_IRQ_CSI0 … #define IPU6_ISYS_UNISPART_IRQ_CSI1 … #define IPU6_ISYS_UNISPART_IRQ_SW … #define IPU6_REG_ISYS_ISL_TOP_IRQ_EDGE … #define IPU6_REG_ISYS_ISL_TOP_IRQ_MASK … #define IPU6_REG_ISYS_ISL_TOP_IRQ_STATUS … #define IPU6_REG_ISYS_ISL_TOP_IRQ_CLEAR … #define IPU6_REG_ISYS_ISL_TOP_IRQ_ENABLE … #define IPU6_REG_ISYS_ISL_TOP_IRQ_LEVEL_NOT_PULSE … #define IPU6_REG_ISYS_CMPR_TOP_IRQ_EDGE … #define IPU6_REG_ISYS_CMPR_TOP_IRQ_MASK … #define IPU6_REG_ISYS_CMPR_TOP_IRQ_STATUS … #define IPU6_REG_ISYS_CMPR_TOP_IRQ_CLEAR … #define IPU6_REG_ISYS_CMPR_TOP_IRQ_ENABLE … #define IPU6_REG_ISYS_CMPR_TOP_IRQ_LEVEL_NOT_PULSE … /* CDC Burst collector thresholds for isys - 3 FIFOs i = 0..2 */ #define IPU6_REG_ISYS_CDC_THRESHOLD(i) … #define IPU6_CSI_IRQ_NUM_PER_PIPE … #define IPU6SE_ISYS_CSI_PORT_NUM … #define IPU6_ISYS_CSI_PORT_NUM … #define IPU6_ISYS_CSI_PORT_IRQ(irq_num) … /* PKG DIR OFFSET in IMR in secure mode */ #define IPU6_PKG_DIR_IMR_OFFSET … #define IPU6_ISYS_REG_SPC_STATUS_CTRL … #define IPU6_ISYS_SPC_STATUS_START … #define IPU6_ISYS_SPC_STATUS_RUN … #define IPU6_ISYS_SPC_STATUS_READY … #define IPU6_ISYS_SPC_STATUS_CTRL_ICACHE_INVALIDATE … #define IPU6_ISYS_SPC_STATUS_ICACHE_PREFETCH … #define IPU6_PSYS_REG_SPC_STATUS_CTRL … #define IPU6_PSYS_REG_SPC_START_PC … #define IPU6_PSYS_REG_SPC_ICACHE_BASE … #define IPU6_REG_PSYS_INFO_SEG_0_CONFIG_ICACHE_MASTER … #define IPU6_PSYS_SPC_STATUS_START … #define IPU6_PSYS_SPC_STATUS_RUN … #define IPU6_PSYS_SPC_STATUS_READY … #define IPU6_PSYS_SPC_STATUS_CTRL_ICACHE_INVALIDATE … #define IPU6_PSYS_SPC_STATUS_ICACHE_PREFETCH … #define IPU6_PSYS_REG_SPP0_STATUS_CTRL … #define IPU6_INFO_ENABLE_SNOOP … #define IPU6_INFO_DEC_FORCE_FLUSH … #define IPU6_INFO_DEC_PASS_THROUGH … #define IPU6_INFO_ZLW … #define IPU6_INFO_REQUEST_DESTINATION_IOSF … #define IPU6_INFO_IMR_BASE … #define IPU6_INFO_IMR_DESTINED … #define IPU6_INFO_REQUEST_DESTINATION_PRIMARY … /* * s2m_pixel_soc_pixel_remapping is dedicated for the enabling of the * pixel s2m remp ability.Remap here means that s2m rearange the order * of the pixels in each 4 pixels group. * For examle, mirroring remping means that if input's 4 first pixels * are 1 2 3 4 then in output we should see 4 3 2 1 in this 4 first pixels. * 0xE4 is from s2m MAS document. It means no remapping. */ #define S2M_PIXEL_SOC_PIXEL_REMAPPING_FLAG_NO_REMAPPING … /* * csi_be_soc_pixel_remapping is for the enabling of the pixel remapping. * This remapping is exactly like the stream2mmio remapping. */ #define CSI_BE_SOC_PIXEL_REMAPPING_FLAG_NO_REMAPPING … #define IPU6_REG_DMA_TOP_AB_GROUP1_BASE_ADDR … #define IPU6_REG_DMA_TOP_AB_GROUP2_BASE_ADDR … #define IPU6_REG_DMA_TOP_AB_RING_MIN_OFFSET(n) … #define IPU6_REG_DMA_TOP_AB_RING_MAX_OFFSET(n) … #define IPU6_REG_DMA_TOP_AB_RING_ACCESS_OFFSET(n) … enum ipu6_device_ab_group1_target_id { … }; enum nci_ab_access_mode { … }; /* IRQ-related registers in PSYS */ #define IPU6_REG_PSYS_GPDEV_IRQ_EDGE … #define IPU6_REG_PSYS_GPDEV_IRQ_MASK … #define IPU6_REG_PSYS_GPDEV_IRQ_STATUS … #define IPU6_REG_PSYS_GPDEV_IRQ_CLEAR … #define IPU6_REG_PSYS_GPDEV_IRQ_ENABLE … #define IPU6_REG_PSYS_GPDEV_IRQ_LEVEL_NOT_PULSE … /* There are 8 FW interrupts, n = 0..7 */ #define IPU6_PSYS_GPDEV_FWIRQ0 … #define IPU6_PSYS_GPDEV_FWIRQ1 … #define IPU6_PSYS_GPDEV_FWIRQ2 … #define IPU6_PSYS_GPDEV_FWIRQ3 … #define IPU6_PSYS_GPDEV_FWIRQ4 … #define IPU6_PSYS_GPDEV_FWIRQ5 … #define IPU6_PSYS_GPDEV_FWIRQ6 … #define IPU6_PSYS_GPDEV_FWIRQ7 … #define IPU6_PSYS_GPDEV_IRQ_FWIRQ(n) … #define IPU6_REG_PSYS_GPDEV_FWIRQ(n) … #endif /* IPU6_PLATFORM_REGS_H */
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