// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2013--2024 Intel Corporation */ #include <linux/atomic.h> #include <linux/bitfield.h> #include <linux/bits.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/err.h> #include <linux/io.h> #include <linux/minmax.h> #include <linux/sprintf.h> #include <media/media-entity.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-device.h> #include <media/v4l2-event.h> #include <media/v4l2-subdev.h> #include "ipu6-bus.h" #include "ipu6-isys.h" #include "ipu6-isys-csi2.h" #include "ipu6-isys-subdev.h" #include "ipu6-platform-isys-csi2-reg.h" static const u32 csi2_supported_codes[] = …; /* * Strings corresponding to CSI-2 receiver errors are here. * Corresponding macros are defined in the header file. */ static const struct ipu6_csi2_error dphy_rx_errors[] = …; s64 ipu6_isys_csi2_get_link_freq(struct ipu6_isys_csi2 *csi2) { … } static int csi2_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, struct v4l2_event_subscription *sub) { … } static const struct v4l2_subdev_core_ops csi2_sd_core_ops = …; /* * The input system CSI2+ receiver has several * parameters affecting the receiver timings. These depend * on the MIPI bus frequency F in Hz (sensor transmitter rate) * as follows: * register value = (A/1e9 + B * UI) / COUNT_ACC * where * UI = 1 / (2 * F) in seconds * COUNT_ACC = counter accuracy in seconds * COUNT_ACC = 0.125 ns = 1 / 8 ns, ACCINV = 8. * * A and B are coefficients from the table below, * depending whether the register minimum or maximum value is * calculated. * Minimum Maximum * Clock lane A B A B * reg_rx_csi_dly_cnt_termen_clane 0 0 38 0 * reg_rx_csi_dly_cnt_settle_clane 95 -8 300 -16 * Data lanes * reg_rx_csi_dly_cnt_termen_dlane0 0 0 35 4 * reg_rx_csi_dly_cnt_settle_dlane0 85 -2 145 -6 * reg_rx_csi_dly_cnt_termen_dlane1 0 0 35 4 * reg_rx_csi_dly_cnt_settle_dlane1 85 -2 145 -6 * reg_rx_csi_dly_cnt_termen_dlane2 0 0 35 4 * reg_rx_csi_dly_cnt_settle_dlane2 85 -2 145 -6 * reg_rx_csi_dly_cnt_termen_dlane3 0 0 35 4 * reg_rx_csi_dly_cnt_settle_dlane3 85 -2 145 -6 * * We use the minimum values of both A and B. */ #define DIV_SHIFT … #define CSI2_ACCINV … static u32 calc_timing(s32 a, s32 b, s64 link_freq, s32 accinv) { … } static int ipu6_isys_csi2_calc_timing(struct ipu6_isys_csi2 *csi2, struct ipu6_isys_csi2_timing *timing, s32 accinv) { … } void ipu6_isys_register_errors(struct ipu6_isys_csi2 *csi2) { … } void ipu6_isys_csi2_error(struct ipu6_isys_csi2 *csi2) { … } static int ipu6_isys_csi2_set_stream(struct v4l2_subdev *sd, const struct ipu6_isys_csi2_timing *timing, unsigned int nlanes, int enable) { … } static int ipu6_isys_csi2_enable_streams(struct v4l2_subdev *sd, struct v4l2_subdev_state *state, u32 pad, u64 streams_mask) { … } static int ipu6_isys_csi2_disable_streams(struct v4l2_subdev *sd, struct v4l2_subdev_state *state, u32 pad, u64 streams_mask) { … } static int ipu6_isys_csi2_set_sel(struct v4l2_subdev *sd, struct v4l2_subdev_state *state, struct v4l2_subdev_selection *sel) { … } static int ipu6_isys_csi2_get_sel(struct v4l2_subdev *sd, struct v4l2_subdev_state *state, struct v4l2_subdev_selection *sel) { … } static const struct v4l2_subdev_pad_ops csi2_sd_pad_ops = …; static const struct v4l2_subdev_ops csi2_sd_ops = …; static const struct media_entity_operations csi2_entity_ops = …; void ipu6_isys_csi2_cleanup(struct ipu6_isys_csi2 *csi2) { … } int ipu6_isys_csi2_init(struct ipu6_isys_csi2 *csi2, struct ipu6_isys *isys, void __iomem *base, unsigned int index) { … } void ipu6_isys_csi2_sof_event_by_stream(struct ipu6_isys_stream *stream) { … } void ipu6_isys_csi2_eof_event_by_stream(struct ipu6_isys_stream *stream) { … } int ipu6_isys_csi2_get_remote_desc(u32 source_stream, struct ipu6_isys_csi2 *csi2, struct media_entity *source_entity, struct v4l2_mbus_frame_desc_entry *entry) { … }
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