linux/drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2013--2024 Intel Corporation
 */

#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/device.h>
#include <linux/io.h>

#include "ipu6-bus.h"
#include "ipu6-isys.h"
#include "ipu6-isys-csi2.h"
#include "ipu6-platform-isys-csi2-reg.h"

/* only use BB0, BB2, BB4, and BB6 on PHY0 */
#define IPU6SE_ISYS_PHY_BB_NUM …
#define IPU6SE_ISYS_PHY_0_BASE …

#define PHY_CPHY_DLL_OVRD(x) …
#define PHY_CPHY_RX_CONTROL1(x) …
#define PHY_DPHY_CFG(x) …
#define PHY_BB_AFE_CONFIG(x) …

/*
 * use port_cfg to configure that which data lanes used
 * +---------+     +------+ +-----+
 * | port0 x4<-----|      | |     |
 * |         |     | port | |     |
 * | port1 x2<-----|      | |     |
 * |         |     |      <-| PHY |
 * | port2 x4<-----|      | |     |
 * |         |     |config| |     |
 * | port3 x2<-----|      | |     |
 * +---------+     +------+ +-----+
 */
static const unsigned int csi2_port_cfg[][3] = …;

/* port, nlanes, bbindex, portcfg */
static const unsigned int phy_port_cfg[][4] = …;

static void ipu6_isys_csi2_phy_config_by_port(struct ipu6_isys *isys,
					      unsigned int port,
					      unsigned int nlanes)
{ … }

static void ipu6_isys_csi2_rx_control(struct ipu6_isys *isys)
{ … }

static int ipu6_isys_csi2_set_port_cfg(struct ipu6_isys *isys,
				       unsigned int port, unsigned int nlanes)
{ … }

static void
ipu6_isys_csi2_set_timing(struct ipu6_isys *isys,
			  const struct ipu6_isys_csi2_timing *timing,
			  unsigned int port, unsigned int nlanes)
{ … }

#define DPHY_TIMER_INCR …
int ipu6_isys_jsl_phy_set_power(struct ipu6_isys *isys,
				struct ipu6_isys_csi2_config *cfg,
				const struct ipu6_isys_csi2_timing *timing,
				bool on)
{ … }