linux/drivers/media/pci/intel/ipu6/ipu6-isys-dwc-phy.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2013--2024 Intel Corporation
 */

#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/iopoll.h>
#include <linux/math64.h>

#include "ipu6-bus.h"
#include "ipu6-isys.h"
#include "ipu6-platform-isys-csi2-reg.h"

#define IPU6_DWC_DPHY_BASE(i) …
#define IPU6_DWC_DPHY_RSTZ …
#define IPU6_DWC_DPHY_SHUTDOWNZ …
#define IPU6_DWC_DPHY_HSFREQRANGE …
#define IPU6_DWC_DPHY_CFGCLKFREQRANGE …
#define IPU6_DWC_DPHY_TEST_IFC_ACCESS_MODE …
#define IPU6_DWC_DPHY_TEST_IFC_REQ …
#define IPU6_DWC_DPHY_TEST_IFC_REQ_COMPLETION …
#define IPU6_DWC_DPHY_DFT_CTRL0 …
#define IPU6_DWC_DPHY_DFT_CTRL1 …
#define IPU6_DWC_DPHY_DFT_CTRL2 …

/*
 * test IFC request definition:
 * - req: 0 for read, 1 for write
 * - 12 bits address
 * - 8bits data (will ignore for read)
 * --24----16------4-----0
 * --|-data-|-addr-|-req-|
 */
#define IFC_REQ(req, addr, data) …

#define TEST_IFC_REQ_READ …
#define TEST_IFC_REQ_WRITE …
#define TEST_IFC_REQ_RESET …

#define TEST_IFC_ACCESS_MODE_FSM …
#define TEST_IFC_ACCESS_MODE_IFC_CTL …

enum phy_fsm_state { … };

static void dwc_dphy_write(struct ipu6_isys *isys, u32 phy_id, u32 addr,
			   u32 data)
{ … }

static u32 dwc_dphy_read(struct ipu6_isys *isys, u32 phy_id, u32 addr)
{ … }

static void dwc_dphy_write_mask(struct ipu6_isys *isys, u32 phy_id, u32 addr,
				u32 data, u8 shift, u8 width)
{ … }

static u32 __maybe_unused dwc_dphy_read_mask(struct ipu6_isys *isys, u32 phy_id,
					     u32 addr, u8 shift,  u8 width)
{ … }

#define DWC_DPHY_TIMEOUT …
static int dwc_dphy_ifc_read(struct ipu6_isys *isys, u32 phy_id, u32 addr,
			     u32 *val)
{ … }

static int dwc_dphy_ifc_write(struct ipu6_isys *isys, u32 phy_id, u32 addr,
			      u32 data)
{ … }

static void dwc_dphy_ifc_write_mask(struct ipu6_isys *isys, u32 phy_id,
				    u32 addr, u32 data, u8 shift, u8 width)
{ … }

static u32 dwc_dphy_ifc_read_mask(struct ipu6_isys *isys, u32 phy_id, u32 addr,
				  u8 shift, u8 width)
{ … }

static int dwc_dphy_pwr_up(struct ipu6_isys *isys, u32 phy_id)
{ … }

struct dwc_dphy_freq_range { … };

#define DPHY_FREQ_RANGE_NUM …
#define DPHY_FREQ_RANGE_INVALID_INDEX …
static const struct dwc_dphy_freq_range freqranges[DPHY_FREQ_RANGE_NUM] = …;

static u16 get_hsfreq_by_mbps(u32 mbps)
{ … }

static int ipu6_isys_dwc_phy_config(struct ipu6_isys *isys,
				    u32 phy_id, u32 mbps)
{ … }

static void ipu6_isys_dwc_phy_aggr_setup(struct ipu6_isys *isys, u32 master,
					 u32 slave, u32 mbps)
{ … }

#define PHY_E …
static int ipu6_isys_dwc_phy_powerup_ack(struct ipu6_isys *isys, u32 phy_id)
{ … }

static void ipu6_isys_dwc_phy_reset(struct ipu6_isys *isys, u32 phy_id)
{ … }

int ipu6_isys_dwc_phy_set_power(struct ipu6_isys *isys,
				struct ipu6_isys_csi2_config *cfg,
				const struct ipu6_isys_csi2_timing *timing,
				bool on)
{ … }