// SPDX-License-Identifier: GPL-2.0 /* * camss-vfe-170.c * * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v170 * * Copyright (C) 2020-2021 Linaro Ltd. */ #include <linux/interrupt.h> #include <linux/io.h> #include <linux/iopoll.h> #include "camss.h" #include "camss-vfe.h" #define VFE_HW_VERSION … #define VFE_GLOBAL_RESET_CMD … #define GLOBAL_RESET_CMD_CORE … #define GLOBAL_RESET_CMD_CAMIF … #define GLOBAL_RESET_CMD_BUS … #define GLOBAL_RESET_CMD_BUS_BDG … #define GLOBAL_RESET_CMD_REGISTER … #define GLOBAL_RESET_CMD_PM … #define GLOBAL_RESET_CMD_BUS_MISR … #define GLOBAL_RESET_CMD_TESTGEN … #define GLOBAL_RESET_CMD_DSP … #define GLOBAL_RESET_CMD_IDLE_CGC … #define GLOBAL_RESET_CMD_RDI0 … #define GLOBAL_RESET_CMD_RDI1 … #define GLOBAL_RESET_CMD_RDI2 … #define GLOBAL_RESET_CMD_RDI3 … #define GLOBAL_RESET_CMD_VFE_DOMAIN … #define GLOBAL_RESET_CMD_RESET_BYPASS … #define VFE_CORE_CFG … #define CFG_PIXEL_PATTERN_YCBYCR … #define CFG_PIXEL_PATTERN_YCRYCB … #define CFG_PIXEL_PATTERN_CBYCRY … #define CFG_PIXEL_PATTERN_CRYCBY … #define CFG_COMPOSITE_REG_UPDATE_EN … #define VFE_IRQ_CMD … #define CMD_GLOBAL_CLEAR … #define VFE_IRQ_MASK_0 … #define MASK_0_CAMIF_SOF … #define MASK_0_CAMIF_EOF … #define MASK_0_RDI_REG_UPDATE(n) … #define MASK_0_IMAGE_MASTER_n_PING_PONG(n) … #define MASK_0_IMAGE_COMPOSITE_DONE_n(n) … #define MASK_0_RESET_ACK … #define VFE_IRQ_MASK_1 … #define MASK_1_CAMIF_ERROR … #define MASK_1_VIOLATION … #define MASK_1_BUS_BDG_HALT_ACK … #define MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(n) … #define MASK_1_RDI_SOF(n) … #define VFE_IRQ_CLEAR_0 … #define VFE_IRQ_CLEAR_1 … #define VFE_IRQ_STATUS_0 … #define STATUS_0_CAMIF_SOF … #define STATUS_0_RDI_REG_UPDATE(n) … #define STATUS_0_IMAGE_MASTER_PING_PONG(n) … #define STATUS_0_IMAGE_COMPOSITE_DONE(n) … #define STATUS_0_RESET_ACK … #define VFE_IRQ_STATUS_1 … #define STATUS_1_VIOLATION … #define STATUS_1_BUS_BDG_HALT_ACK … #define STATUS_1_RDI_SOF(n) … #define VFE_VIOLATION_STATUS … #define VFE_CAMIF_CMD … #define CMD_CLEAR_CAMIF_STATUS … #define VFE_CAMIF_CFG … #define CFG_VSYNC_SYNC_EDGE … #define VSYNC_ACTIVE_HIGH … #define VSYNC_ACTIVE_LOW … #define CFG_HSYNC_SYNC_EDGE … #define HSYNC_ACTIVE_HIGH … #define HSYNC_ACTIVE_LOW … #define CFG_VFE_SUBSAMPLE_ENABLE … #define CFG_BUS_SUBSAMPLE_ENABLE … #define CFG_VFE_OUTPUT_EN … #define CFG_BUS_OUTPUT_EN … #define CFG_BINNING_EN … #define CFG_FRAME_BASED_EN … #define CFG_RAW_CROP_EN … #define VFE_REG_UPDATE_CMD … #define REG_UPDATE_RDI(n) … #define VFE_BUS_IRQ_MASK(n) … #define VFE_BUS_IRQ_CLEAR(n) … #define VFE_BUS_IRQ_STATUS(n) … #define STATUS0_COMP_RESET_DONE … #define STATUS0_COMP_REG_UPDATE0_DONE … #define STATUS0_COMP_REG_UPDATE1_DONE … #define STATUS0_COMP_REG_UPDATE2_DONE … #define STATUS0_COMP_REG_UPDATE3_DONE … #define STATUS0_COMP_REG_UPDATE_DONE(n) … #define STATUS0_COMP0_BUF_DONE … #define STATUS0_COMP1_BUF_DONE … #define STATUS0_COMP2_BUF_DONE … #define STATUS0_COMP3_BUF_DONE … #define STATUS0_COMP4_BUF_DONE … #define STATUS0_COMP5_BUF_DONE … #define STATUS0_COMP_BUF_DONE(n) … #define STATUS0_COMP_ERROR … #define STATUS0_COMP_OVERWRITE … #define STATUS0_OVERFLOW … #define STATUS0_VIOLATION … /* WM_CLIENT_BUF_DONE defined for buffers 0:19 */ #define STATUS1_WM_CLIENT_BUF_DONE(n) … #define STATUS1_EARLY_DONE … #define STATUS2_DUAL_COMP0_BUF_DONE … #define STATUS2_DUAL_COMP1_BUF_DONE … #define STATUS2_DUAL_COMP2_BUF_DONE … #define STATUS2_DUAL_COMP3_BUF_DONE … #define STATUS2_DUAL_COMP4_BUF_DONE … #define STATUS2_DUAL_COMP5_BUF_DONE … #define STATUS2_DUAL_COMP_BUF_DONE(n) … #define STATUS2_DUAL_COMP_ERROR … #define STATUS2_DUAL_COMP_OVERWRITE … #define VFE_BUS_IRQ_CLEAR_GLOBAL … #define VFE_BUS_WM_DEBUG_STATUS_CFG … #define DEBUG_STATUS_CFG_STATUS0(n) … #define DEBUG_STATUS_CFG_STATUS1(n) … #define VFE_BUS_WM_ADDR_SYNC_FRAME_HEADER … #define VFE_BUS_WM_ADDR_SYNC_NO_SYNC … #define BUS_VER2_MAX_CLIENTS … #define WM_ADDR_NO_SYNC_DEFAULT_VAL … #define VFE_BUS_WM_CGC_OVERRIDE … #define WM_CGC_OVERRIDE_ALL … #define VFE_BUS_WM_TEST_BUS_CTRL … #define VFE_BUS_WM_STATUS0(n) … #define VFE_BUS_WM_STATUS1(n) … #define VFE_BUS_WM_CFG(n) … #define WM_CFG_EN … #define WM_CFG_MODE … #define MODE_QCOM_PLAIN … #define MODE_MIPI_RAW … #define WM_CFG_VIRTUALFRAME … #define VFE_BUS_WM_HEADER_ADDR(n) … #define VFE_BUS_WM_HEADER_CFG(n) … #define VFE_BUS_WM_IMAGE_ADDR(n) … #define VFE_BUS_WM_IMAGE_ADDR_OFFSET(n) … #define VFE_BUS_WM_BUFFER_WIDTH_CFG(n) … #define WM_BUFFER_DEFAULT_WIDTH … #define VFE_BUS_WM_BUFFER_HEIGHT_CFG(n) … #define VFE_BUS_WM_PACKER_CFG(n) … #define VFE_BUS_WM_STRIDE(n) … #define WM_STRIDE_DEFAULT_STRIDE … #define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) … #define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) … #define VFE_BUS_WM_FRAMEDROP_PERIOD(n) … #define VFE_BUS_WM_FRAMEDROP_PATTERN(n) … #define VFE_BUS_WM_FRAME_INC(n) … #define VFE_BUS_WM_BURST_LIMIT(n) … static u32 vfe_hw_version(struct vfe_device *vfe) { … } static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits) { … } static void vfe_global_reset(struct vfe_device *vfe) { … } static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line) { … } static void vfe_wm_stop(struct vfe_device *vfe, u8 wm) { … } static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr, struct vfe_line *line) { … } static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) { … } static inline void vfe_reg_update_clear(struct vfe_device *vfe, enum vfe_line_id line_id) { … } static void vfe_enable_irq_common(struct vfe_device *vfe) { … } static void vfe_isr_halt_ack(struct vfe_device *vfe) { … } static void vfe_isr_read(struct vfe_device *vfe, u32 *status0, u32 *status1) { … } static void vfe_violation_read(struct vfe_device *vfe) { … } /* * vfe_isr - VFE module interrupt handler * @irq: Interrupt line * @dev: VFE device * * Return IRQ_HANDLED on success */ static irqreturn_t vfe_isr(int irq, void *dev) { … } /* * vfe_halt - Trigger halt on VFE module and wait to complete * @vfe: VFE device * * Return 0 on success or a negative error code otherwise */ static int vfe_halt(struct vfe_device *vfe) { … } static int vfe_get_output(struct vfe_line *line) { … } static int vfe_enable_output(struct vfe_line *line) { … } /* * vfe_enable - Enable streaming on VFE line * @line: VFE line * * Return 0 on success or a negative error code otherwise */ static int vfe_enable(struct vfe_line *line) { … } /* * vfe_isr_sof - Process start of frame interrupt * @vfe: VFE Device * @line_id: VFE line */ static void vfe_isr_sof(struct vfe_device *vfe, enum vfe_line_id line_id) { … } /* * vfe_isr_reg_update - Process reg update interrupt * @vfe: VFE Device * @line_id: VFE line */ static void vfe_isr_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) { … } /* * vfe_isr_wm_done - Process write master done interrupt * @vfe: VFE Device * @wm: Write master id */ static void vfe_isr_wm_done(struct vfe_device *vfe, u8 wm) { … } /* * vfe_queue_buffer - Add empty buffer * @vid: Video device structure * @buf: Buffer to be enqueued * * Add an empty buffer - depending on the current number of buffers it will be * put in pending buffer queue or directly given to the hardware to be filled. * * Return 0 on success or a negative error code otherwise */ static int vfe_queue_buffer(struct camss_video *vid, struct camss_buffer *buf) { … } static const struct vfe_isr_ops vfe_isr_ops_170 = …; static const struct camss_video_ops vfe_video_ops_170 = …; static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe) { … } const struct vfe_hw_ops vfe_ops_170 = …;
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