linux/drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright(c) 2024 Intel Corporation */
#ifndef ADF_GEN2_HW_CSR_DATA_H_
#define ADF_GEN2_HW_CSR_DATA_H_

#include <linux/bitops.h>
#include "adf_accel_devices.h"

#define ADF_BANK_INT_SRC_SEL_MASK_0 …
#define ADF_BANK_INT_SRC_SEL_MASK_X …
#define ADF_RING_CSR_RING_CONFIG …
#define ADF_RING_CSR_RING_LBASE …
#define ADF_RING_CSR_RING_UBASE …
#define ADF_RING_CSR_RING_HEAD …
#define ADF_RING_CSR_RING_TAIL …
#define ADF_RING_CSR_E_STAT …
#define ADF_RING_CSR_INT_FLAG …
#define ADF_RING_CSR_INT_SRCSEL …
#define ADF_RING_CSR_INT_SRCSEL_2 …
#define ADF_RING_CSR_INT_COL_EN …
#define ADF_RING_CSR_INT_COL_CTL …
#define ADF_RING_CSR_INT_FLAG_AND_COL …
#define ADF_RING_CSR_INT_COL_CTL_ENABLE …
#define ADF_RING_BUNDLE_SIZE …
#define ADF_ARB_REG_SLOT …
#define ADF_ARB_RINGSRVARBEN_OFFSET …

#define BUILD_RING_BASE_ADDR(addr, size) …
#define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) …
#define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) …
#define READ_CSR_E_STAT(csr_base_addr, bank) …
#define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) …
#define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) …

#define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) …
#define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) …
#define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) …
#define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) …
#define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) …
#define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) …
#define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) …

#define WRITE_CSR_RING_SRV_ARB_EN(csr_addr, index, value) …

void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops);

#endif