linux/drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c

// SPDX-License-Identifier: GPL-2.0-only
/* Copyright(c) 2024 Intel Corporation */
#include <linux/types.h>
#include "adf_gen2_hw_csr_data.h"

static u64 build_csr_ring_base_addr(dma_addr_t addr, u32 size)
{ … }

static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring)
{ … }

static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring,
				u32 value)
{ … }

static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring)
{ … }

static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring,
				u32 value)
{ … }

static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank)
{ … }

static void write_csr_ring_config(void __iomem *csr_base_addr, u32 bank,
				  u32 ring, u32 value)
{ … }

static void write_csr_ring_base(void __iomem *csr_base_addr, u32 bank, u32 ring,
				dma_addr_t addr)
{ … }

static void write_csr_int_flag(void __iomem *csr_base_addr, u32 bank, u32 value)
{ … }

static void write_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank)
{ … }

static void write_csr_int_col_en(void __iomem *csr_base_addr, u32 bank,
				 u32 value)
{ … }

static void write_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank,
				  u32 value)
{ … }

static void write_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank,
				       u32 value)
{ … }

static void write_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank,
				      u32 value)
{ … }

void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops)
{ … }
EXPORT_SYMBOL_GPL(…);