// SPDX-License-Identifier: MIT /* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #include "dm_services.h" #include "dc.h" #include "dcn32/dcn32_init.h" #include "resource.h" #include "include/irq_service_interface.h" #include "dcn32_resource.h" #include "dcn20/dcn20_resource.h" #include "dcn30/dcn30_resource.h" #include "dcn10/dcn10_ipp.h" #include "dcn30/dcn30_hubbub.h" #include "dcn31/dcn31_hubbub.h" #include "dcn32/dcn32_hubbub.h" #include "dcn32/dcn32_mpc.h" #include "dcn32/dcn32_hubp.h" #include "irq/dcn32/irq_service_dcn32.h" #include "dcn32/dcn32_dpp.h" #include "dcn32/dcn32_optc.h" #include "dcn20/dcn20_hwseq.h" #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" #include "dcn20/dcn20_dsc.h" #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dcn30/dcn30_dio_stream_encoder.h" #include "dcn32/dcn32_dio_stream_encoder.h" #include "dcn31/dcn31_hpo_dp_stream_encoder.h" #include "dcn31/dcn31_hpo_dp_link_encoder.h" #include "dcn32/dcn32_hpo_dp_link_encoder.h" #include "dcn31/dcn31_apg.h" #include "dcn31/dcn31_dio_link_encoder.h" #include "dcn32/dcn32_dio_link_encoder.h" #include "dce/dce_clock_source.h" #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" #include "virtual/virtual_stream_encoder.h" #include "dml/display_mode_vba.h" #include "dcn32/dcn32_dccg.h" #include "dcn10/dcn10_resource.h" #include "link.h" #include "dcn31/dcn31_panel_cntl.h" #include "dcn30/dcn30_dwb.h" #include "dcn32/dcn32_mmhubbub.h" #include "dcn/dcn_3_2_0_offset.h" #include "dcn/dcn_3_2_0_sh_mask.h" #include "nbio/nbio_4_3_0_offset.h" #include "reg_helper.h" #include "dce/dmub_abm.h" #include "dce/dmub_psr.h" #include "dce/dce_aux.h" #include "dce/dce_i2c.h" #include "dml/dcn30/display_mode_vba_30.h" #include "vm_helper.h" #include "dcn20/dcn20_vmid.h" #include "dml/dcn32/dcn32_fpu.h" #include "dc_state_priv.h" #include "dml2/dml2_wrapper.h" #define DC_LOGGER_INIT(logger) … enum dcn32_clk_src_array_id { … }; /* begin ********************* * macros to expend register list macro defined in HW object header file */ /* DCN */ #define BASE_INNER(seg) … #define BASE(seg) … #define SR(reg_name) … #define SR_ARR(reg_name, id) … #define SR_ARR_INIT(reg_name, id, value) … #define SRI(reg_name, block, id) … #define SRI_ARR(reg_name, block, id) … #define SR_ARR_I2C(reg_name, id) … #define SRI_ARR_I2C(reg_name, block, id) … #define SRI_ARR_ALPHABET(reg_name, block, index, id) … #define SRI2(reg_name, block, id) … #define SRI2_ARR(reg_name, block, id) … #define SRIR(var_name, reg_name, block, id) … #define SRII(reg_name, block, id) … #define SRII_ARR_2(reg_name, block, id, inst) … #define SRII_MPC_RMU(reg_name, block, id) … #define SRII_DWB(reg_name, temp_name, block, id) … #define SF_DWB2(reg_name, block, id, field_name, post_fix) … #define DCCG_SRII(reg_name, block, id) … #define VUPDATE_SRII(reg_name, block, id) … /* NBIO */ #define NBIO_BASE_INNER(seg) … #define NBIO_BASE(seg) … #define NBIO_SR(reg_name) … #define NBIO_SR_ARR(reg_name, id) … #undef CTX #define CTX … #define REG(reg_name) … static struct bios_registers bios_regs; #define bios_regs_init() … #define clk_src_regs_init(index, pllid) … static struct dce110_clk_src_regs clk_src_regs[5]; static const struct dce110_clk_src_shift cs_shift = …; static const struct dce110_clk_src_mask cs_mask = …; #define abm_regs_init(id) … static struct dce_abm_registers abm_regs[4]; static const struct dce_abm_shift abm_shift = …; static const struct dce_abm_mask abm_mask = …; #define audio_regs_init(id) … static struct dce_audio_registers audio_regs[5]; #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh) … static const struct dce_audio_shift audio_shift = …; static const struct dce_audio_mask audio_mask = …; #define vpg_regs_init(id) … static struct dcn30_vpg_registers vpg_regs[10]; static const struct dcn30_vpg_shift vpg_shift = …; static const struct dcn30_vpg_mask vpg_mask = …; #define afmt_regs_init(id) … static struct dcn30_afmt_registers afmt_regs[6]; static const struct dcn30_afmt_shift afmt_shift = …; static const struct dcn30_afmt_mask afmt_mask = …; #define apg_regs_init(id) … static struct dcn31_apg_registers apg_regs[4]; static const struct dcn31_apg_shift apg_shift = …; static const struct dcn31_apg_mask apg_mask = …; #define stream_enc_regs_init(id) … static struct dcn10_stream_enc_registers stream_enc_regs[5]; static const struct dcn10_stream_encoder_shift se_shift = …; static const struct dcn10_stream_encoder_mask se_mask = …; #define aux_regs_init(id) … static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; #define hpd_regs_init(id) … static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; #define link_regs_init(id, phyid) … /*DPCS_DCN31_REG_LIST(id),*/ \ static struct dcn10_link_enc_registers link_enc_regs[5]; static const struct dcn10_link_enc_shift le_shift = …; static const struct dcn10_link_enc_mask le_mask = …; #define hpo_dp_stream_encoder_reg_init(id) … static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = …; static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = …; #define hpo_dp_link_encoder_reg_init(id) … /*DCN3_1_RDPCSTX_REG_LIST(0),*/ /*DCN3_1_RDPCSTX_REG_LIST(1),*/ /*DCN3_1_RDPCSTX_REG_LIST(2),*/ /*DCN3_1_RDPCSTX_REG_LIST(3),*/ static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2]; static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = …; static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = …; #define dpp_regs_init(id) … static struct dcn3_dpp_registers dpp_regs[4]; static const struct dcn3_dpp_shift tf_shift = …; static const struct dcn3_dpp_mask tf_mask = …; #define opp_regs_init(id) … static struct dcn20_opp_registers opp_regs[4]; static const struct dcn20_opp_shift opp_shift = …; static const struct dcn20_opp_mask opp_mask = …; #define aux_engine_regs_init(id) … static struct dce110_aux_registers aux_engine_regs[5]; static const struct dce110_aux_registers_shift aux_shift = …; static const struct dce110_aux_registers_mask aux_mask = …; #define dwbc_regs_dcn3_init(id) … static struct dcn30_dwbc_registers dwbc30_regs[1]; static const struct dcn30_dwbc_shift dwbc30_shift = …; static const struct dcn30_dwbc_mask dwbc30_mask = …; #define mcif_wb_regs_dcn3_init(id) … static struct dcn30_mmhubbub_registers mcif_wb30_regs[1]; static const struct dcn30_mmhubbub_shift mcif_wb30_shift = …; static const struct dcn30_mmhubbub_mask mcif_wb30_mask = …; #define dsc_regsDCN20_init(id) … static struct dcn20_dsc_registers dsc_regs[4]; static const struct dcn20_dsc_shift dsc_shift = …; static const struct dcn20_dsc_mask dsc_mask = …; static struct dcn30_mpc_registers mpc_regs; #define dcn_mpc_regs_init() … static const struct dcn30_mpc_shift mpc_shift = …; static const struct dcn30_mpc_mask mpc_mask = …; #define optc_regs_init(id) … static struct dcn_optc_registers optc_regs[4]; static const struct dcn_optc_shift optc_shift = …; static const struct dcn_optc_mask optc_mask = …; #define hubp_regs_init(id) … static struct dcn_hubp2_registers hubp_regs[4]; static const struct dcn_hubp2_shift hubp_shift = …; static const struct dcn_hubp2_mask hubp_mask = …; static struct dcn_hubbub_registers hubbub_reg; #define hubbub_reg_init() … static const struct dcn_hubbub_shift hubbub_shift = …; static const struct dcn_hubbub_mask hubbub_mask = …; static struct dccg_registers dccg_regs; #define dccg_regs_init() … static const struct dccg_shift dccg_shift = …; static const struct dccg_mask dccg_mask = …; #define SRII2(reg_name_pre, reg_name_post, id) … #define HWSEQ_DCN32_REG_LIST() … static struct dce_hwseq_registers hwseq_reg; #define hwseq_reg_init() … #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh) … static const struct dce_hwseq_shift hwseq_shift = …; static const struct dce_hwseq_mask hwseq_mask = …; #define vmid_regs_init(id) … static struct dcn_vmid_registers vmid_regs[16]; static const struct dcn20_vmid_shift vmid_shifts = …; static const struct dcn20_vmid_mask vmid_masks = …; static const struct resource_caps res_cap_dcn32 = …; static const struct dc_plane_cap plane_cap = …; static const struct dc_debug_options debug_defaults_drv = …; static struct dce_aux *dcn32_aux_engine_create( struct dc_context *ctx, uint32_t inst) { … } #define i2c_inst_regs_init(id) … static struct dce_i2c_registers i2c_hw_regs[5]; static const struct dce_i2c_shift i2c_shifts = …; static const struct dce_i2c_mask i2c_masks = …; static struct dce_i2c_hw *dcn32_i2c_hw_create( struct dc_context *ctx, uint32_t inst) { … } static struct clock_source *dcn32_clock_source_create( struct dc_context *ctx, struct dc_bios *bios, enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) { … } static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx) { … } static struct hubp *dcn32_hubp_create( struct dc_context *ctx, uint32_t inst) { … } static void dcn32_dpp_destroy(struct dpp **dpp) { … } static struct dpp *dcn32_dpp_create( struct dc_context *ctx, uint32_t inst) { … } static struct mpc *dcn32_mpc_create( struct dc_context *ctx, int num_mpcc, int num_rmu) { … } static struct output_pixel_processor *dcn32_opp_create( struct dc_context *ctx, uint32_t inst) { … } static struct timing_generator *dcn32_timing_generator_create( struct dc_context *ctx, uint32_t instance) { … } static const struct encoder_feature_support link_enc_feature = …; static struct link_encoder *dcn32_link_encoder_create( struct dc_context *ctx, const struct encoder_init_data *enc_init_data) { … } struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data) { … } static void read_dce_straps( struct dc_context *ctx, struct resource_straps *straps) { … } static struct audio *dcn32_create_audio( struct dc_context *ctx, unsigned int inst) { … } static struct vpg *dcn32_vpg_create( struct dc_context *ctx, uint32_t inst) { … } static struct afmt *dcn32_afmt_create( struct dc_context *ctx, uint32_t inst) { … } static struct apg *dcn31_apg_create( struct dc_context *ctx, uint32_t inst) { … } static struct stream_encoder *dcn32_stream_encoder_create( enum engine_id eng_id, struct dc_context *ctx) { … } static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create( enum engine_id eng_id, struct dc_context *ctx) { … } static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create( uint8_t inst, struct dc_context *ctx) { … } static struct dce_hwseq *dcn32_hwseq_create( struct dc_context *ctx) { … } static const struct resource_create_funcs res_create_funcs = …; static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) { … } static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { … } static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { … } static struct display_stream_compressor *dcn32_dsc_create( struct dc_context *ctx, uint32_t inst) { … } static void dcn32_destroy_resource_pool(struct resource_pool **pool) { … } bool dcn32_acquire_post_bldn_3dlut( struct resource_context *res_ctx, const struct resource_pool *pool, int mpcc_id, struct dc_3dlut **lut, struct dc_transfer_func **shaper) { … } bool dcn32_release_post_bldn_3dlut( struct resource_context *res_ctx, const struct resource_pool *pool, struct dc_3dlut **lut, struct dc_transfer_func **shaper) { … } static void dcn32_enable_phantom_plane(struct dc *dc, struct dc_state *context, struct dc_stream_state *phantom_stream, unsigned int dc_pipe_idx) { … } static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, unsigned int pipe_cnt, unsigned int dc_pipe_idx) { … } /* TODO: Input to this function should indicate which pipe indexes (or streams) * require a phantom pipe / stream */ void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, unsigned int pipe_cnt, unsigned int index) { … } static bool dml1_validate(struct dc *dc, struct dc_state *context, bool fast_validate) { … } bool dcn32_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate) { … } int dcn32_populate_dml_pipes_from_context( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, bool fast_validate) { … } unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned int total_size_in_mall_bytes) { … } static struct dc_cap_funcs cap_funcs = …; void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) { … } static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) { … } static struct resource_funcs dcn32_res_pool_funcs = …; static uint32_t read_pipe_fuses(struct dc_context *ctx) { … } static bool dcn32_resource_construct( uint8_t num_virtual_links, struct dc *dc, struct dcn32_resource_pool *pool) { … } struct resource_pool *dcn32_create_resource_pool( const struct dc_init_data *init_data, struct dc *dc) { … } /* * Find the most optimal free pipe from res_ctx, which could be used as a * secondary dpp pipe for input opp head pipe. * * a free pipe - a pipe in input res_ctx not yet used for any streams or * planes. * secondary dpp pipe - a pipe gets inserted to a head OPP pipe's MPC blending * tree. This is typical used for rendering MPO planes or additional offset * areas in MPCC combine. * * Hardware Transition Minimization Algorithm for Finding a Secondary DPP Pipe * ------------------------------------------------------------------------- * * PROBLEM: * * 1. There is a hardware limitation that a secondary DPP pipe cannot be * transferred from one MPC blending tree to the other in a single frame. * Otherwise it could cause glitches on the screen. * * For instance, we cannot transition from state 1 to state 2 in one frame. This * is because PIPE1 is transferred from PIPE0's MPC blending tree over to * PIPE2's MPC blending tree, which is not supported by hardware. * To support this transition we need to first remove PIPE1 from PIPE0's MPC * blending tree in one frame and then insert PIPE1 to PIPE2's MPC blending tree * in the next frame. This is not optimal as it will delay the flip for two * frames. * * State 1: * PIPE0 -- secondary DPP pipe --> (PIPE1) * PIPE2 -- secondary DPP pipe --> NONE * * State 2: * PIPE0 -- secondary DPP pipe --> NONE * PIPE2 -- secondary DPP pipe --> (PIPE1) * * 2. We want to in general minimize the unnecessary changes in pipe topology. * If a pipe is already added in current blending tree and there are no changes * to plane topology, we don't want to swap it with another free pipe * unnecessarily in every update. Powering up and down a pipe would require a * full update which delays the flip for 1 frame. If we use the original pipe * we don't have to toggle its power. So we can flip faster. */ int dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe( const struct resource_context *cur_res_ctx, struct resource_context *new_res_ctx, const struct resource_pool *pool, const struct pipe_ctx *new_opp_head) { … } static struct pipe_ctx *find_idle_secondary_pipe_check_mpo( struct resource_context *res_ctx, const struct resource_pool *pool, const struct pipe_ctx *primary_pipe) { … } static struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer( struct dc_state *state, const struct resource_pool *pool, struct dc_stream_state *stream, const struct pipe_ctx *head_pipe) { … } static int find_optimal_free_pipe_as_secondary_opp_head( const struct resource_context *cur_res_ctx, struct resource_context *new_res_ctx, const struct resource_pool *pool, const struct pipe_ctx *new_otg_master) { … } struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe( const struct dc_state *cur_ctx, struct dc_state *new_ctx, const struct resource_pool *pool, const struct pipe_ctx *opp_head_pipe) { … } struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head( const struct dc_state *cur_ctx, struct dc_state *new_ctx, const struct resource_pool *pool, const struct pipe_ctx *otg_master) { … } unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans) { … }
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