dcn10_optc.c | Explore in Territory

/*
 * Copyright 2012-15 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */


#include "reg_helper.h"
#include "dcn10_optc.h"
#include "dc.h"
#include "dc_trace.h"

#define REG(reg) …

#define CTX …

#undef FN
#define FN(reg_name, field_name) …

#define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN …

/**
 * apply_front_porch_workaround() - This is a workaround for a bug that has
 *                                  existed since R5xx and has not been fixed
 *                                  keep Front porch at minimum 2 for Interlaced
 *                                  mode or 1 for progressive.
 *
 * @timing: Timing parameters used to configure DCN blocks.
 */
static void apply_front_porch_workaround(struct dc_crtc_timing *timing)
{ … }

void optc1_program_global_sync(
		struct timing_generator *optc,
		int vready_offset,
		int vstartup_start,
		int vupdate_offset,
		int vupdate_width)
{ … }

static void optc1_disable_stereo(struct timing_generator *optc)
{ … }

void optc1_setup_vertical_interrupt0(
		struct timing_generator *optc,
		uint32_t start_line,
		uint32_t end_line)
{ … }

void optc1_setup_vertical_interrupt1(
		struct timing_generator *optc,
		uint32_t start_line)
{ … }

void optc1_setup_vertical_interrupt2(
		struct timing_generator *optc,
		uint32_t start_line)
{ … }

/**
 * optc1_program_timing() - used by mode timing set Program
 *                          CRTC Timing Registers - OTG_H_*,
 *                          OTG_V_*, Pixel repetition.
 *                          Including SYNC. Call BIOS command table to program Timings.
 *
 * @optc: timing_generator instance.
 * @dc_crtc_timing: Timing parameters used to configure DCN blocks.
 * @vready_offset: Vready's starting position.
 * @vstartup_start: Vstartup period.
 * @vupdate_offset: Vupdate starting position.
 * @vupdate_width: Vupdate duration.
 * @signal: DC signal types.
 * @use_vbios: to program timings from BIOS command table.
 *
 */
void optc1_program_timing(
	struct timing_generator *optc,
	const struct dc_crtc_timing *dc_crtc_timing,
	int vready_offset,
	int vstartup_start,
	int vupdate_offset,
	int vupdate_width,
	const enum signal_type signal,
	bool use_vbios)
{ … }

/**
 * optc1_set_vtg_params - Set Vertical Timing Generator (VTG) parameters
 *
 * @optc: timing_generator struct used to extract the optc parameters
 * @dc_crtc_timing: Timing parameters configured
 * @program_fp2: Boolean value indicating if FP2 will be programmed or not
 *
 * OTG is responsible for generating the global sync signals, including
 * vertical timing information for each HUBP in the dcfclk domain. Each VTG is
 * associated with one OTG that provides HUBP with vertical timing information
 * (i.e., there is 1:1 correspondence between OTG and VTG). This function is
 * responsible for setting the OTG parameters to the VTG during the pipe
 * programming.
 */
void optc1_set_vtg_params(struct timing_generator *optc,
		const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2)
{ … }

void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable)
{ … }

/**
 * optc1_set_timing_double_buffer() - DRR double buffering control
 *
 * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN,
 * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers.
 *
 * @optc: timing_generator instance.
 * @enable: Enable DRR double buffering control if true, disable otherwise.
 *
 * Options: any time,  start of frame, dp start of frame (range timing)
 */
void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable)
{ … }

/**
 * optc1_unblank_crtc() - Call ASIC Control Object to UnBlank CRTC.
 *
 * @optc: timing_generator instance.
 */
static void optc1_unblank_crtc(struct timing_generator *optc)
{ … }

/**
 * optc1_blank_crtc() - Call ASIC Control Object to Blank CRTC.
 *
 * @optc: timing_generator instance.
 */

static void optc1_blank_crtc(struct timing_generator *optc)
{ … }

void optc1_set_blank(struct timing_generator *optc,
		bool enable_blanking)
{ … }

bool optc1_is_blanked(struct timing_generator *optc)
{ … }

void optc1_enable_optc_clock(struct timing_generator *optc, bool enable)
{ … }

/**
 * optc1_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator.
 *
 * @optc: timing_generator instance.
 */
static bool optc1_enable_crtc(struct timing_generator *optc)
{ … }

/* disable_crtc - call ASIC Control Object to disable Timing generator. */
bool optc1_disable_crtc(struct timing_generator *optc)
{ … }


void optc1_program_blank_color(
		struct timing_generator *optc,
		const struct tg_color *black_color)
{ … }

bool optc1_validate_timing(
	struct timing_generator *optc,
	const struct dc_crtc_timing *timing)
{ … }

/*
 * get_vblank_counter
 *
 * @brief
 * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which
 * holds the counter of frames.
 *
 * @param
 * struct timing_generator *optc - [in] timing generator which controls the
 * desired CRTC
 *
 * @return
 * Counter of frames, which should equal to number of vblanks.
 */
uint32_t optc1_get_vblank_counter(struct timing_generator *optc)
{ … }

void optc1_lock(struct timing_generator *optc)
{ … }

void optc1_unlock(struct timing_generator *optc)
{ … }

void optc1_get_position(struct timing_generator *optc,
		struct crtc_position *position)
{ … }

bool optc1_is_counter_moving(struct timing_generator *optc)
{ … }

bool optc1_did_triggered_reset_occur(
	struct timing_generator *optc)
{ … }

void optc1_disable_reset_trigger(struct timing_generator *optc)
{ … }

void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst)
{ … }

void optc1_enable_crtc_reset(
		struct timing_generator *optc,
		int source_tg_inst,
		struct crtc_trigger_info *crtc_tp)
{ … }

void optc1_wait_for_state(struct timing_generator *optc,
		enum crtc_state state)
{ … }

void optc1_set_early_control(
	struct timing_generator *optc,
	uint32_t early_cntl)
{ … }


void optc1_set_static_screen_control(
	struct timing_generator *optc,
	uint32_t event_triggers,
	uint32_t num_frames)
{ … }

static void optc1_setup_manual_trigger(struct timing_generator *optc)
{ … }

static void optc1_program_manual_trigger(struct timing_generator *optc)
{ … }

/**
 * optc1_set_drr() - Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
 *
 * @optc: timing_generator instance.
 * @params: parameters used for Dynamic Refresh Rate.
 */
void optc1_set_drr(
	struct timing_generator *optc,
	const struct drr_params *params)
{ … }

void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max)
{ … }

static void optc1_set_test_pattern(
	struct timing_generator *optc,
	/* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
	 * because this is not DP-specific (which is probably somewhere in DP
	 * encoder) */
	enum controller_dp_test_pattern test_pattern,
	enum dc_color_depth color_depth)
{ … }

void optc1_get_crtc_scanoutpos(
	struct timing_generator *optc,
	uint32_t *v_blank_start,
	uint32_t *v_blank_end,
	uint32_t *h_position,
	uint32_t *v_position)
{ … }

static void optc1_enable_stereo(struct timing_generator *optc,
	const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
{ … }

void optc1_program_stereo(struct timing_generator *optc,
	const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
{ … }


bool optc1_is_stereo_left_eye(struct timing_generator *optc)
{ … }

bool optc1_get_hw_timing(struct timing_generator *tg,
		struct dc_crtc_timing *hw_crtc_timing)
{ … }


void optc1_read_otg_state(struct optc *optc1,
		struct dcn_otg_state *s)
{ … }

bool optc1_get_otg_active_size(struct timing_generator *optc,
		uint32_t *otg_active_width,
		uint32_t *otg_active_height)
{ … }

void optc1_clear_optc_underflow(struct timing_generator *optc)
{ … }

void optc1_tg_init(struct timing_generator *optc)
{ … }

bool optc1_is_tg_enabled(struct timing_generator *optc)
{ … }

bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)
{ … }

bool optc1_configure_crc(struct timing_generator *optc,
			  const struct crc_params *params)
{ … }

/**
 * optc1_get_crc - Capture CRC result per component
 *
 * @optc: timing_generator instance.
 * @r_cr: 16-bit primary CRC signature for red data.
 * @g_y: 16-bit primary CRC signature for green data.
 * @b_cb: 16-bit primary CRC signature for blue data.
 *
 * This function reads the CRC signature from the OPTC registers. Notice that
 * we have three registers to keep the CRC result per color component (RGB).
 *
 * Returns:
 * If CRC is disabled, return false; otherwise, return true, and the CRC
 * results in the parameters.
 */
bool optc1_get_crc(struct timing_generator *optc,
		   uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
{ … }

/* "Container" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this:
 *
 * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as
 *   container rate.
 *
 * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be
 *   halved to maintain the correct pixel rate.
 *
 * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied
 *   to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well.
 *
 */
bool optc1_is_two_pixels_per_container(const struct dc_crtc_timing *timing)
{ … }

static const struct timing_generator_funcs dcn10_tg_funcs = …;

void dcn10_timing_generator_init(struct optc *optc1)
{ … }
linux/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
