linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

/*
 * Copyright 2012-15 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include "reg_helper.h"
#include "dcn20_optc.h"
#include "dc.h"

#define REG(reg)

#define CTX

#undef FN
#define FN(reg_name, field_name)

/**
 * optc2_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator.
 *
 * @optc: timing_generator instance.
 *
 * Return: If CRTC is enabled, return true.
 *
 */
bool optc2_enable_crtc(struct timing_generator *optc)
{}

/**
 * optc2_set_gsl() - Assign OTG to GSL groups,
 *                   set one of the OTGs to be master & rest are slaves
 *
 * @optc: timing_generator instance.
 * @params: pointer to gsl_params
 */
void optc2_set_gsl(struct timing_generator *optc,
		   const struct gsl_params *params)
{}


void optc2_set_gsl_source_select(
		struct timing_generator *optc,
		int group_idx,
		uint32_t gsl_ready_signal)
{}

/* Set DSC-related configuration.
 *   dsc_mode: 0 disables DSC, other values enable DSC in specified format
 *   sc_bytes_per_pixel: Bytes per pixel in u3.28 format
 *   dsc_slice_width: Slice width in pixels
 */
void optc2_set_dsc_config(struct timing_generator *optc,
					enum optc_dsc_mode dsc_mode,
					uint32_t dsc_bytes_per_pixel,
					uint32_t dsc_slice_width)
{}

/* Get DSC-related configuration.
 *   dsc_mode: 0 disables DSC, other values enable DSC in specified format
 */
void optc2_get_dsc_status(struct timing_generator *optc,
					uint32_t *dsc_mode)
{}

void optc2_set_odm_bypass(struct timing_generator *optc,
		const struct dc_crtc_timing *dc_crtc_timing)
{}

void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
		int segment_width, int last_segment_width)
{}

void optc2_get_optc_source(struct timing_generator *optc,
		uint32_t *num_of_src_opp,
		uint32_t *src_opp_id_0,
		uint32_t *src_opp_id_1)
{}

static void optc2_set_dwb_source(struct timing_generator *optc,
				 uint32_t dwb_pipe_inst)
{}

static void optc2_align_vblanks(
	struct timing_generator *optc_master,
	struct timing_generator *optc_slave,
	uint32_t master_pixel_clock_100Hz,
	uint32_t slave_pixel_clock_100Hz,
	uint8_t master_clock_divider,
	uint8_t slave_clock_divider)
{}

void optc2_triplebuffer_lock(struct timing_generator *optc)
{}

void optc2_triplebuffer_unlock(struct timing_generator *optc)
{}

void optc2_lock_doublebuffer_enable(struct timing_generator *optc)
{}

void optc2_lock_doublebuffer_disable(struct timing_generator *optc)
{}

void optc2_setup_manual_trigger(struct timing_generator *optc)
{}

void optc2_program_manual_trigger(struct timing_generator *optc)
{}

bool optc2_configure_crc(struct timing_generator *optc,
			  const struct crc_params *params)
{}


void optc2_get_last_used_drr_vtotal(struct timing_generator *optc, uint32_t *refresh_rate)
{}

static struct timing_generator_funcs dcn20_tg_funcs =;

void dcn20_timing_generator_init(struct optc *optc1)
{}