/* * Copyright 2015 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ /* The caprices of the preprocessor require that this be declared right here */ #define CREATE_TRACE_POINTS #include "dm_services_types.h" #include "dc.h" #include "link_enc_cfg.h" #include "dc/inc/core_types.h" #include "dal_asic_id.h" #include "dmub/dmub_srv.h" #include "dc/inc/hw/dmcu.h" #include "dc/inc/hw/abm.h" #include "dc/dc_dmub_srv.h" #include "dc/dc_edid_parser.h" #include "dc/dc_stat.h" #include "dc/dc_state.h" #include "amdgpu_dm_trace.h" #include "dpcd_defs.h" #include "link/protocols/link_dpcd.h" #include "link_service_types.h" #include "link/protocols/link_dp_capability.h" #include "link/protocols/link_ddc.h" #include "vid.h" #include "amdgpu.h" #include "amdgpu_display.h" #include "amdgpu_ucode.h" #include "atom.h" #include "amdgpu_dm.h" #include "amdgpu_dm_plane.h" #include "amdgpu_dm_crtc.h" #include "amdgpu_dm_hdcp.h" #include <drm/display/drm_hdcp_helper.h> #include "amdgpu_dm_wb.h" #include "amdgpu_pm.h" #include "amdgpu_atombios.h" #include "amd_shared.h" #include "amdgpu_dm_irq.h" #include "dm_helpers.h" #include "amdgpu_dm_mst_types.h" #if defined(CONFIG_DEBUG_FS) #include "amdgpu_dm_debugfs.h" #endif #include "amdgpu_dm_psr.h" #include "amdgpu_dm_replay.h" #include "ivsrcid/ivsrcid_vislands30.h" #include <linux/backlight.h> #include <linux/module.h> #include <linux/moduleparam.h> #include <linux/types.h> #include <linux/pm_runtime.h> #include <linux/pci.h> #include <linux/power_supply.h> #include <linux/firmware.h> #include <linux/component.h> #include <linux/dmi.h> #include <linux/sort.h> #include <drm/display/drm_dp_mst_helper.h> #include <drm/display/drm_hdmi_helper.h> #include <drm/drm_atomic.h> #include <drm/drm_atomic_uapi.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_blend.h> #include <drm/drm_fixed.h> #include <drm/drm_fourcc.h> #include <drm/drm_edid.h> #include <drm/drm_eld.h> #include <drm/drm_vblank.h> #include <drm/drm_audio_component.h> #include <drm/drm_gem_atomic_helper.h> #include <acpi/video.h> #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" #include "dcn/dcn_1_0_offset.h" #include "dcn/dcn_1_0_sh_mask.h" #include "soc15_hw_ip.h" #include "soc15_common.h" #include "vega10_ip_offset.h" #include "gc/gc_11_0_0_offset.h" #include "gc/gc_11_0_0_sh_mask.h" #include "modules/inc/mod_freesync.h" #include "modules/power/power_helpers.h" #define FIRMWARE_RENOIR_DMUB … MODULE_FIRMWARE(…); #define FIRMWARE_SIENNA_CICHLID_DMUB … MODULE_FIRMWARE(…); #define FIRMWARE_NAVY_FLOUNDER_DMUB … MODULE_FIRMWARE(…); #define FIRMWARE_GREEN_SARDINE_DMUB … MODULE_FIRMWARE(…); #define FIRMWARE_VANGOGH_DMUB … MODULE_FIRMWARE(…); #define FIRMWARE_DIMGREY_CAVEFISH_DMUB … MODULE_FIRMWARE(…); #define FIRMWARE_BEIGE_GOBY_DMUB … MODULE_FIRMWARE(…); #define FIRMWARE_YELLOW_CARP_DMUB … MODULE_FIRMWARE(…); #define FIRMWARE_DCN_314_DMUB … MODULE_FIRMWARE(…); #define FIRMWARE_DCN_315_DMUB … MODULE_FIRMWARE(…); #define FIRMWARE_DCN316_DMUB … MODULE_FIRMWARE(…); #define FIRMWARE_DCN_V3_2_0_DMCUB … MODULE_FIRMWARE(…); #define FIRMWARE_DCN_V3_2_1_DMCUB … MODULE_FIRMWARE(…); #define FIRMWARE_RAVEN_DMCU … MODULE_FIRMWARE(…); #define FIRMWARE_NAVI12_DMCU … MODULE_FIRMWARE(…); #define FIRMWARE_DCN_35_DMUB … MODULE_FIRMWARE(…); #define FIRMWARE_DCN_351_DMUB … MODULE_FIRMWARE(…); #define FIRMWARE_DCN_401_DMUB … MODULE_FIRMWARE(…); /* Number of bytes in PSP header for firmware. */ #define PSP_HEADER_BYTES … /* Number of bytes in PSP footer for firmware. */ #define PSP_FOOTER_BYTES … /** * DOC: overview * * The AMDgpu display manager, **amdgpu_dm** (or even simpler, * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM * requests into DC requests, and DC responses into DRM responses. * * The root control structure is &struct amdgpu_display_manager. */ /* basic init/fini API */ static int amdgpu_dm_init(struct amdgpu_device *adev); static void amdgpu_dm_fini(struct amdgpu_device *adev); static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector); static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link) { … } static void update_subconnector_property(struct amdgpu_dm_connector *aconnector) { … } /* * initializes drm_device display related structures, based on the information * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, * drm_encoder, drm_mode_config * * Returns 0 on success */ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); /* removes and deallocates the drm structures, created by the above function */ static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, struct amdgpu_dm_connector *amdgpu_dm_connector, u32 link_index, struct amdgpu_encoder *amdgpu_encoder); static int amdgpu_dm_encoder_init(struct drm_device *dev, struct amdgpu_encoder *aencoder, uint32_t link_index); static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); static int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); static void handle_hpd_rx_irq(void *param); static bool is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, struct drm_crtc_state *new_crtc_state); /* * dm_vblank_get_counter * * @brief * Get counter for number of vertical blanks * * @param * struct amdgpu_device *adev - [in] desired amdgpu device * int disp_idx - [in] which CRTC to get the counter from * * @return * Counter for vertical blanks */ static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) { … } static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, u32 *vbl, u32 *position) { … } static bool dm_is_idle(void *handle) { … } static int dm_wait_for_idle(void *handle) { … } static bool dm_check_soft_reset(void *handle) { … } static int dm_soft_reset(void *handle) { … } static struct amdgpu_crtc * get_crtc_by_otg_inst(struct amdgpu_device *adev, int otg_inst) { … } static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, struct dm_crtc_state *new_state) { … } /* * DC will program planes with their z-order determined by their ordering * in the dc_surface_updates array. This comparator is used to sort them * by descending zpos. */ static int dm_plane_layer_index_cmp(const void *a, const void *b) { … } /** * update_planes_and_stream_adapter() - Send planes to be updated in DC * * DC has a generic way to update planes and stream via * dc_update_planes_and_stream function; however, DM might need some * adjustments and preparation before calling it. This function is a wrapper * for the dc_update_planes_and_stream that does any required configuration * before passing control to DC. * * @dc: Display Core control structure * @update_type: specify whether it is FULL/MEDIUM/FAST update * @planes_count: planes count to update * @stream: stream state * @stream_update: stream update * @array_of_surface_update: dc surface update pointer * */ static inline bool update_planes_and_stream_adapter(struct dc *dc, int update_type, int planes_count, struct dc_stream_state *stream, struct dc_stream_update *stream_update, struct dc_surface_update *array_of_surface_update) { … } /** * dm_pflip_high_irq() - Handle pageflip interrupt * @interrupt_params: ignored * * Handles the pageflip interrupt by notifying all interested parties * that the pageflip has been completed. */ static void dm_pflip_high_irq(void *interrupt_params) { … } static void dm_vupdate_high_irq(void *interrupt_params) { … } /** * dm_crtc_high_irq() - Handles CRTC interrupt * @interrupt_params: used for determining the CRTC instance * * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK * event handler. */ static void dm_crtc_high_irq(void *interrupt_params) { … } #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) /** * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for * DCN generation ASICs * @interrupt_params: interrupt parameters * * Used to set crc window/read out crc value at vertical line 0 position */ static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params) { … } #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */ /** * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command. * @adev: amdgpu_device pointer * @notify: dmub notification structure * * Dmub AUX or SET_CONFIG command completion processing callback * Copies dmub notification to DM which is to be read by AUX command. * issuing thread and also signals the event to wake up the thread. */ static void dmub_aux_setconfig_callback(struct amdgpu_device *adev, struct dmub_notification *notify) { … } /** * dmub_hpd_callback - DMUB HPD interrupt processing callback. * @adev: amdgpu_device pointer * @notify: dmub notification structure * * Dmub Hpd interrupt processing callback. Gets displayindex through the * ink index and calls helper to do the processing. */ static void dmub_hpd_callback(struct amdgpu_device *adev, struct dmub_notification *notify) { … } /** * register_dmub_notify_callback - Sets callback for DMUB notify * @adev: amdgpu_device pointer * @type: Type of dmub notification * @callback: Dmub interrupt callback function * @dmub_int_thread_offload: offload indicator * * API to register a dmub callback handler for a dmub notification * Also sets indicator whether callback processing to be offloaded. * to dmub interrupt handling thread * Return: true if successfully registered, false if there is existing registration */ static bool register_dmub_notify_callback(struct amdgpu_device *adev, enum dmub_notification_type type, dmub_notify_interrupt_callback_t callback, bool dmub_int_thread_offload) { … } static void dm_handle_hpd_work(struct work_struct *work) { … } #define DMUB_TRACE_MAX_READ … /** * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt * @interrupt_params: used for determining the Outbox instance * * Handles the Outbox Interrupt * event handler. */ static void dm_dmub_outbox1_low_irq(void *interrupt_params) { … } static int dm_set_clockgating_state(void *handle, enum amd_clockgating_state state) { … } static int dm_set_powergating_state(void *handle, enum amd_powergating_state state) { … } /* Prototypes of private functions */ static int dm_early_init(void *handle); /* Allocate memory for FBC compressed data */ static void amdgpu_dm_fbc_init(struct drm_connector *connector) { … } static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, int pipe, bool *enabled, unsigned char *buf, int max_bytes) { … } static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = …; static int amdgpu_dm_audio_component_bind(struct device *kdev, struct device *hda_kdev, void *data) { … } static void amdgpu_dm_audio_component_unbind(struct device *kdev, struct device *hda_kdev, void *data) { … } static const struct component_ops amdgpu_dm_audio_component_bind_ops = …; static int amdgpu_dm_audio_init(struct amdgpu_device *adev) { … } static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) { … } static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) { … } static int dm_dmub_hw_init(struct amdgpu_device *adev) { … } static void dm_dmub_hw_resume(struct amdgpu_device *adev) { … } static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) { … } static void force_connector_state( struct amdgpu_dm_connector *aconnector, enum drm_connector_force force_state) { … } static void dm_handle_hpd_rx_offload_work(struct work_struct *work) { … } static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc) { … } struct amdgpu_stutter_quirk { … }; static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = …; static bool dm_should_disable_stutter(struct pci_dev *pdev) { … } static const struct dmi_system_id hpd_disconnect_quirk_table[] = …; static void retrieve_dmi_info(struct amdgpu_display_manager *dm) { … } void* dm_allocate_gpu_mem( struct amdgpu_device *adev, enum dc_gpu_mem_alloc_type type, size_t size, long long *addr) { … } static enum dmub_status dm_dmub_send_vbios_gpint_command(struct amdgpu_device *adev, enum dmub_gpint_command command_code, uint16_t param, uint32_t timeout_us) { … } static struct dml2_soc_bb *dm_dmub_get_vbios_bounding_box(struct amdgpu_device *adev) { … } static int amdgpu_dm_init(struct amdgpu_device *adev) { … } static int amdgpu_dm_early_fini(void *handle) { … } static void amdgpu_dm_fini(struct amdgpu_device *adev) { … } static int load_dmcu_fw(struct amdgpu_device *adev) { … } static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address) { … } static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address, uint32_t value) { … } static int dm_dmub_sw_init(struct amdgpu_device *adev) { … } static int dm_sw_init(void *handle) { … } static int dm_sw_fini(void *handle) { … } static int detect_mst_link_for_all_connectors(struct drm_device *dev) { … } static int dm_late_init(void *handle) { … } static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) { … } static void s3_handle_mst(struct drm_device *dev, bool suspend) { … } static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) { … } /** * dm_hw_init() - Initialize DC device * @handle: The base driver device containing the amdgpu_dm device. * * Initialize the &struct amdgpu_display_manager device. This involves calling * the initializers of each DM component, then populating the struct with them. * * Although the function implies hardware initialization, both hardware and * software are initialized here. Splitting them out to their relevant init * hooks is a future TODO item. * * Some notable things that are initialized here: * * - Display Core, both software and hardware * - DC modules that we need (freesync and color management) * - DRM software states * - Interrupt sources and handlers * - Vblank support * - Debug FS entries, if enabled */ static int dm_hw_init(void *handle) { … } /** * dm_hw_fini() - Teardown DC device * @handle: The base driver device containing the amdgpu_dm device. * * Teardown components within &struct amdgpu_display_manager that require * cleanup. This involves cleaning up the DRM device, DC, and any modules that * were loaded. Also flush IRQ workqueues and disable them. */ static int dm_hw_fini(void *handle) { … } static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, struct dc_state *state, bool enable) { … } static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) { … } static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm) { … } static int dm_suspend(void *handle) { … } struct drm_connector * amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, struct drm_crtc *crtc) { … } static void emulated_link_detect(struct dc_link *link) { … } static void dm_gpureset_commit_state(struct dc_state *dc_state, struct amdgpu_display_manager *dm) { … } static int dm_resume(void *handle) { … } /** * DOC: DM Lifecycle * * DM (and consequently DC) is registered in the amdgpu base driver as a IP * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to * the base driver's device list to be initialized and torn down accordingly. * * The functions to do so are provided as hooks in &struct amd_ip_funcs. */ static const struct amd_ip_funcs amdgpu_dm_funcs = …; const struct amdgpu_ip_block_version dm_ip_block = …; /** * DOC: atomic * * *WIP* */ static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = …; static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = …; static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) { … } void amdgpu_dm_update_connector_after_detect( struct amdgpu_dm_connector *aconnector) { … } static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) { … } static void handle_hpd_irq(void *param) { … } static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq, union hpd_irq_data hpd_irq_data) { … } static void handle_hpd_rx_irq(void *param) { … } static int register_hpd_handlers(struct amdgpu_device *adev) { … } #if defined(CONFIG_DRM_AMD_DC_SI) /* Register IRQ sources and initialize IRQ callbacks */ static int dce60_register_irq_handlers(struct amdgpu_device *adev) { … } #endif /* Register IRQ sources and initialize IRQ callbacks */ static int dce110_register_irq_handlers(struct amdgpu_device *adev) { … } /* Register IRQ sources and initialize IRQ callbacks */ static int dcn10_register_irq_handlers(struct amdgpu_device *adev) { … } /* Register Outbox IRQ sources and initialize IRQ callbacks */ static int register_outbox_irq_handlers(struct amdgpu_device *adev) { … } /* * Acquires the lock for the atomic state object and returns * the new atomic state. * * This should only be called during atomic check. */ int dm_atomic_get_state(struct drm_atomic_state *state, struct dm_atomic_state **dm_state) { … } static struct dm_atomic_state * dm_atomic_get_new_state(struct drm_atomic_state *state) { … } static struct drm_private_state * dm_atomic_duplicate_state(struct drm_private_obj *obj) { … } static void dm_atomic_destroy_state(struct drm_private_obj *obj, struct drm_private_state *state) { … } static struct drm_private_state_funcs dm_atomic_state_funcs = …; static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) { … } #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT … #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT … #define AUX_BL_DEFAULT_TRANSITION_TIME_MS … static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, int bl_idx) { … } static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, unsigned int *min, unsigned int *max) { … } static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps, uint32_t brightness) { … } static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps, uint32_t brightness) { … } static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, int bl_idx, u32 user_brightness) { … } static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) { … } static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, int bl_idx) { … } static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) { … } static const struct backlight_ops amdgpu_dm_backlight_ops = …; static void amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector) { … } static int initialize_plane(struct amdgpu_display_manager *dm, struct amdgpu_mode_info *mode_info, int plane_id, enum drm_plane_type plane_type, const struct dc_plane_cap *plane_cap) { … } static void setup_backlight_device(struct amdgpu_display_manager *dm, struct amdgpu_dm_connector *aconnector) { … } static void amdgpu_set_panel_orientation(struct drm_connector *connector); /* * In this architecture, the association * connector -> encoder -> crtc * id not really requried. The crtc and connector will hold the * display_index as an abstraction to use with DAL component * * Returns 0 on success */ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) { … } static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) { … } /****************************************************************************** * amdgpu_display_funcs functions *****************************************************************************/ /* * dm_bandwidth_update - program display watermarks * * @adev: amdgpu_device pointer * * Calculate and program the display watermarks and line buffer allocation. */ static void dm_bandwidth_update(struct amdgpu_device *adev) { … } static const struct amdgpu_display_funcs dm_display_funcs = …; #if defined(CONFIG_DEBUG_KERNEL_DC) static ssize_t s3_debug_store(struct device *device, struct device_attribute *attr, const char *buf, size_t count) { … } DEVICE_ATTR_WO(…); #endif static int dm_init_microcode(struct amdgpu_device *adev) { … } static int dm_early_init(void *handle) { … } static bool modereset_required(struct drm_crtc_state *crtc_state) { … } static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) { … } static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = …; static int fill_plane_color_attributes(const struct drm_plane_state *plane_state, const enum surface_pixel_format format, enum dc_color_space *color_space) { … } static int fill_dc_plane_info_and_addr(struct amdgpu_device *adev, const struct drm_plane_state *plane_state, const u64 tiling_flags, struct dc_plane_info *plane_info, struct dc_plane_address *address, bool tmz_surface, bool force_disable_dcc) { … } static int fill_dc_plane_attributes(struct amdgpu_device *adev, struct dc_plane_state *dc_plane_state, struct drm_plane_state *plane_state, struct drm_crtc_state *crtc_state) { … } static inline void fill_dc_dirty_rect(struct drm_plane *plane, struct rect *dirty_rect, int32_t x, s32 y, s32 width, s32 height, int *i, bool ffu) { … } /** * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates * * @plane: DRM plane containing dirty regions that need to be flushed to the eDP * remote fb * @old_plane_state: Old state of @plane * @new_plane_state: New state of @plane * @crtc_state: New state of CRTC connected to the @plane * @flip_addrs: DC flip tracking struct, which also tracts dirty rects * @is_psr_su: Flag indicating whether Panel Self Refresh Selective Update (PSR SU) is enabled. * If PSR SU is enabled and damage clips are available, only the regions of the screen * that have changed will be updated. If PSR SU is not enabled, * or if damage clips are not available, the entire screen will be updated. * @dirty_regions_changed: dirty regions changed * * For PSR SU, DC informs the DMUB uController of dirty rectangle regions * (referred to as "damage clips" in DRM nomenclature) that require updating on * the eDP remote buffer. The responsibility of specifying the dirty regions is * amdgpu_dm's. * * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the * plane with regions that require flushing to the eDP remote buffer. In * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - * implicitly provide damage clips without any client support via the plane * bounds. */ static void fill_dc_dirty_rects(struct drm_plane *plane, struct drm_plane_state *old_plane_state, struct drm_plane_state *new_plane_state, struct drm_crtc_state *crtc_state, struct dc_flip_addrs *flip_addrs, bool is_psr_su, bool *dirty_regions_changed) { … } static void update_stream_scaling_settings(const struct drm_display_mode *mode, const struct dm_connector_state *dm_state, struct dc_stream_state *stream) { … } static enum dc_color_depth convert_color_depth_from_display_info(const struct drm_connector *connector, bool is_y420, int requested_bpc) { … } static enum dc_aspect_ratio get_aspect_ratio(const struct drm_display_mode *mode_in) { … } static enum dc_color_space get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, const struct drm_connector_state *connector_state) { … } static enum display_content_type get_output_content_type(const struct drm_connector_state *connector_state) { … } static bool adjust_colour_depth_from_display_info( struct dc_crtc_timing *timing_out, const struct drm_display_info *info) { … } static void fill_stream_properties_from_drm_display_mode( struct dc_stream_state *stream, const struct drm_display_mode *mode_in, const struct drm_connector *connector, const struct drm_connector_state *connector_state, const struct dc_stream_state *old_stream, int requested_bpc) { … } static void fill_audio_info(struct audio_info *audio_info, const struct drm_connector *drm_connector, const struct dc_sink *dc_sink) { … } static void copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, struct drm_display_mode *dst_mode) { … } static void decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, const struct drm_display_mode *native_mode, bool scale_enabled) { … } static struct dc_sink * create_fake_sink(struct dc_link *link) { … } static void set_multisync_trigger_params( struct dc_stream_state *stream) { … } static void set_master_stream(struct dc_stream_state *stream_set[], int stream_count) { … } static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) { … } /** * DOC: FreeSync Video * * When a userspace application wants to play a video, the content follows a * standard format definition that usually specifies the FPS for that format. * The below list illustrates some video format and the expected FPS, * respectively: * * - TV/NTSC (23.976 FPS) * - Cinema (24 FPS) * - TV/PAL (25 FPS) * - TV/NTSC (29.97 FPS) * - TV/NTSC (30 FPS) * - Cinema HFR (48 FPS) * - TV/PAL (50 FPS) * - Commonly used (60 FPS) * - Multiples of 24 (48,72,96 FPS) * * The list of standards video format is not huge and can be added to the * connector modeset list beforehand. With that, userspace can leverage * FreeSync to extends the front porch in order to attain the target refresh * rate. Such a switch will happen seamlessly, without screen blanking or * reprogramming of the output in any other way. If the userspace requests a * modesetting change compatible with FreeSync modes that only differ in the * refresh rate, DC will skip the full update and avoid blink during the * transition. For example, the video player can change the modesetting from * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without * causing any display blink. This same concept can be applied to a mode * setting change. */ static struct drm_display_mode * get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, bool use_probed_modes) { … } static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector) { … } #if defined(CONFIG_DRM_AMD_DC_FP) static void update_dsc_caps(struct amdgpu_dm_connector *aconnector, struct dc_sink *sink, struct dc_stream_state *stream, struct dsc_dec_dpcd_caps *dsc_caps) { … } static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector, struct dc_sink *sink, struct dc_stream_state *stream, struct dsc_dec_dpcd_caps *dsc_caps, uint32_t max_dsc_target_bpp_limit_override) { … } static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, struct dc_sink *sink, struct dc_stream_state *stream, struct dsc_dec_dpcd_caps *dsc_caps) { … } #endif static struct dc_stream_state * create_stream_for_sink(struct drm_connector *connector, const struct drm_display_mode *drm_mode, const struct dm_connector_state *dm_state, const struct dc_stream_state *old_stream, int requested_bpc) { … } static enum drm_connector_status amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) { … } int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, struct drm_connector_state *connector_state, struct drm_property *property, uint64_t val) { … } int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, const struct drm_connector_state *state, struct drm_property *property, uint64_t *val) { … } /** * DOC: panel power savings * * The display manager allows you to set your desired **panel power savings** * level (between 0-4, with 0 representing off), e.g. using the following:: * * # echo 3 > /sys/class/drm/card0-eDP-1/amdgpu/panel_power_savings * * Modifying this value can have implications on color accuracy, so tread * carefully. */ static ssize_t panel_power_savings_show(struct device *device, struct device_attribute *attr, char *buf) { … } static ssize_t panel_power_savings_store(struct device *device, struct device_attribute *attr, const char *buf, size_t count) { … } static DEVICE_ATTR_RW(panel_power_savings); static struct attribute *amdgpu_attrs[] = …; static const struct attribute_group amdgpu_group = …; static bool amdgpu_dm_should_create_sysfs(struct amdgpu_dm_connector *amdgpu_dm_connector) { … } static void amdgpu_dm_connector_unregister(struct drm_connector *connector) { … } static void amdgpu_dm_connector_destroy(struct drm_connector *connector) { … } void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) { … } struct drm_connector_state * amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) { … } static int amdgpu_dm_connector_late_register(struct drm_connector *connector) { … } static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) { … } static const struct drm_connector_funcs amdgpu_dm_connector_funcs = …; static int get_modes(struct drm_connector *connector) { … } static void create_eml_sink(struct amdgpu_dm_connector *aconnector) { … } static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) { … } static enum dc_status dm_validate_stream_and_context(struct dc *dc, struct dc_stream_state *stream) { … } struct dc_stream_state * create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, const struct drm_display_mode *drm_mode, const struct dm_connector_state *dm_state, const struct dc_stream_state *old_stream) { … } enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) { … } static int fill_hdr_info_packet(const struct drm_connector_state *state, struct dc_info_packet *out) { … } static int amdgpu_dm_connector_atomic_check(struct drm_connector *conn, struct drm_atomic_state *state) { … } static const struct drm_connector_helper_funcs amdgpu_dm_connector_helper_funcs = …; static void dm_encoder_helper_disable(struct drm_encoder *encoder) { … } int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) { … } static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { … } const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = …; static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, struct dc_state *dc_state, struct dsc_mst_fairness_vars *vars) { … } static int to_drm_connector_type(enum signal_type st) { … } static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) { … } static void amdgpu_dm_get_native_mode(struct drm_connector *connector) { … } static struct drm_display_mode * amdgpu_dm_create_common_mode(struct drm_encoder *encoder, char *name, int hdisplay, int vdisplay) { … } static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, struct drm_connector *connector) { … } static void amdgpu_set_panel_orientation(struct drm_connector *connector) { … } static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, struct edid *edid) { … } static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector, struct drm_display_mode *mode) { … } static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) { … } static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, struct edid *edid) { … } static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) { … } static const u32 supported_colorspaces = …; void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, struct amdgpu_dm_connector *aconnector, int connector_type, struct dc_link *link, int link_index) { … } static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) { … } static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) { … } static const struct i2c_algorithm amdgpu_dm_i2c_algo = …; static struct amdgpu_i2c_adapter * create_i2c(struct ddc_service *ddc_service, int link_index, int *res) { … } /* * Note: this function assumes that dc_link_detect() was called for the * dc_link which will be represented by this aconnector. */ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, struct amdgpu_dm_connector *aconnector, u32 link_index, struct amdgpu_encoder *aencoder) { … } int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) { … } static int amdgpu_dm_encoder_init(struct drm_device *dev, struct amdgpu_encoder *aencoder, uint32_t link_index) { … } static void manage_dm_interrupts(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc, bool enable) { … } static void dm_update_pflip_irq_state(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc) { … } static bool is_scaling_state_different(const struct dm_connector_state *dm_state, const struct dm_connector_state *old_dm_state) { … } static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state, struct drm_crtc_state *old_crtc_state, struct drm_connector_state *new_conn_state, struct drm_connector_state *old_conn_state, const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w) { … } static void remove_stream(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc, struct dc_stream_state *stream) { … } static void prepare_flip_isr(struct amdgpu_crtc *acrtc) { … } static void update_freesync_state_on_stream( struct amdgpu_display_manager *dm, struct dm_crtc_state *new_crtc_state, struct dc_stream_state *new_stream, struct dc_plane_state *surface, u32 flip_timestamp_in_us) { … } static void update_stream_irq_parameters( struct amdgpu_display_manager *dm, struct dm_crtc_state *new_crtc_state) { … } static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, struct dm_crtc_state *new_state) { … } static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) { … } static inline uint32_t get_mem_type(struct drm_framebuffer *fb) { … } static void amdgpu_dm_update_cursor(struct drm_plane *plane, struct drm_plane_state *old_plane_state, struct dc_stream_update *update) { … } static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, struct drm_device *dev, struct amdgpu_display_manager *dm, struct drm_crtc *pcrtc, bool wait_for_vblank) { … } static void amdgpu_dm_commit_audio(struct drm_device *dev, struct drm_atomic_state *state) { … } /* * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC * @crtc_state: the DRM CRTC state * @stream_state: the DC stream state. * * Copy the mirrored transient state flags from DRM, to DC. It is used to bring * a dc_stream_state's flags in sync with a drm_crtc_state's flags. */ static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, struct dc_stream_state *stream_state) { … } static void dm_clear_writeback(struct amdgpu_display_manager *dm, struct dm_crtc_state *crtc_state) { … } static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, struct dc_state *dc_state) { … } static void dm_set_writeback(struct amdgpu_display_manager *dm, struct dm_crtc_state *crtc_state, struct drm_connector *connector, struct drm_connector_state *new_con_state) { … } /** * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. * @state: The atomic state to commit * * This will tell DC to commit the constructed DC state from atomic_check, * programming the hardware. Any failures here implies a hardware failure, since * atomic check should have filtered anything non-kosher. */ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) { … } static int dm_force_atomic_commit(struct drm_connector *connector) { … } /* * This function handles all cases when set mode does not come upon hotplug. * This includes when a display is unplugged then plugged back into the * same port and when running without usermode desktop manager supprot */ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector) { … } /* * Grabs all modesetting locks to serialize against any blocking commits, * Waits for completion of all non blocking commits. */ static int do_aquire_global_lock(struct drm_device *dev, struct drm_atomic_state *state) { … } static void get_freesync_config_for_crtc( struct dm_crtc_state *new_crtc_state, struct dm_connector_state *new_con_state) { … } static void reset_freesync_config_for_crtc( struct dm_crtc_state *new_crtc_state) { … } static bool is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, struct drm_crtc_state *new_crtc_state) { … } static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) { … } static int dm_update_crtc_state(struct amdgpu_display_manager *dm, struct drm_atomic_state *state, struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state, struct drm_crtc_state *new_crtc_state, bool enable, bool *lock_and_validation_needed) { … } static bool should_reset_plane(struct drm_atomic_state *state, struct drm_plane *plane, struct drm_plane_state *old_plane_state, struct drm_plane_state *new_plane_state) { … } static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, struct drm_plane_state *new_plane_state, struct drm_framebuffer *fb) { … } /* * Helper function for checking the cursor in native mode */ static int dm_check_native_cursor_state(struct drm_crtc *new_plane_crtc, struct drm_plane *plane, struct drm_plane_state *new_plane_state, bool enable) { … } static bool dm_should_update_native_cursor(struct drm_atomic_state *state, struct drm_crtc *old_plane_crtc, struct drm_crtc *new_plane_crtc, bool enable) { … } static int dm_update_plane_state(struct dc *dc, struct drm_atomic_state *state, struct drm_plane *plane, struct drm_plane_state *old_plane_state, struct drm_plane_state *new_plane_state, bool enable, bool *lock_and_validation_needed, bool *is_top_most_overlay) { … } static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state, int *src_w, int *src_h) { … } static void dm_get_plane_scale(struct drm_plane_state *plane_state, int *out_plane_scale_w, int *out_plane_scale_h) { … } /* * The normalized_zpos value cannot be used by this iterator directly. It's only * calculated for enabled planes, potentially causing normalized_zpos collisions * between enabled/disabled planes in the atomic state. We need a unique value * so that the iterator will not generate the same object twice, or loop * indefinitely. */ static inline struct __drm_planes_state *__get_next_zpos( struct drm_atomic_state *state, struct __drm_planes_state *prev) { … } /* * Use the uniqueness of the plane's (zpos, drm obj ID) combination to iterate * by descending zpos, as read from the new plane state. This is the same * ordering as defined by drm_atomic_normalize_zpos(). */ #define for_each_oldnew_plane_in_descending_zpos(__state, plane, old_plane_state, new_plane_state) … static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) { … } /** * DOC: Cursor Modes - Native vs Overlay * * In native mode, the cursor uses a integrated cursor pipe within each DCN hw * plane. It does not require a dedicated hw plane to enable, but it is * subjected to the same z-order and scaling as the hw plane. It also has format * restrictions, a RGB cursor in native mode cannot be enabled within a non-RGB * hw plane. * * In overlay mode, the cursor uses a separate DCN hw plane, and thus has its * own scaling and z-pos. It also has no blending restrictions. It lends to a * cursor behavior more akin to a DRM client's expectations. However, it does * occupy an extra DCN plane, and therefore will only be used if a DCN plane is * available. */ /** * dm_crtc_get_cursor_mode() - Determine the required cursor mode on crtc * @adev: amdgpu device * @state: DRM atomic state * @dm_crtc_state: amdgpu state for the CRTC containing the cursor * @cursor_mode: Returns the required cursor mode on dm_crtc_state * * Get whether the cursor should be enabled in native mode, or overlay mode, on * the dm_crtc_state. * * The cursor should be enabled in overlay mode if there exists an underlying * plane - on which the cursor may be blended - that is either YUV formatted, or * scaled differently from the cursor. * * Since zpos info is required, drm_atomic_normalize_zpos must be called before * calling this function. * * Return: 0 on success, or an error code if getting the cursor plane state * failed. */ static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev, struct drm_atomic_state *state, struct dm_crtc_state *dm_crtc_state, enum amdgpu_dm_cursor_mode *cursor_mode) { … } /** * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. * * @dev: The DRM device * @state: The atomic state to commit * * Validate that the given atomic state is programmable by DC into hardware. * This involves constructing a &struct dc_state reflecting the new hardware * state we wish to commit, then querying DC to see if it is programmable. It's * important not to modify the existing DC state. Otherwise, atomic_check * may unexpectedly commit hardware changes. * * When validating the DC state, it's important that the right locks are * acquired. For full updates case which removes/adds/updates streams on one * CRTC while flipping on another CRTC, acquiring global lock will guarantee * that any such full update commit will wait for completion of any outstanding * flip using DRMs synchronization events. * * Note that DM adds the affected connectors for all CRTCs in state, when that * might not seem necessary. This is because DC stream creation requires the * DC sink, which is tied to the DRM connector state. Cleaning this up should * be possible but non-trivial - a possible TODO item. * * Return: -Error code if validation failed. */ static int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) { … } static bool is_dp_capable_without_timing_msa(struct dc *dc, struct amdgpu_dm_connector *amdgpu_dm_connector) { … } static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm, unsigned int offset, unsigned int total_length, u8 *data, unsigned int length, struct amdgpu_hdmi_vsdb_info *vsdb) { … } static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm, u8 *edid_ext, int len, struct amdgpu_hdmi_vsdb_info *vsdb_info) { … } static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm, u8 *edid_ext, int len, struct amdgpu_hdmi_vsdb_info *vsdb_info) { … } static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, u8 *edid_ext, int len, struct amdgpu_hdmi_vsdb_info *vsdb_info) { … } static void parse_edid_displayid_vrr(struct drm_connector *connector, struct edid *edid) { … } static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) { … } static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) { … } /** * amdgpu_dm_update_freesync_caps - Update Freesync capabilities * * @connector: Connector to query. * @edid: EDID from monitor * * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep * track of some of the display information in the internal data struct used by * amdgpu_dm. This function checks which type of connector we need to set the * FreeSync parameters. */ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, struct edid *edid) { … } void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) { … } static inline void amdgpu_dm_exit_ips_for_hw_access(struct dc *dc) { … } void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, u32 value, const char *func_name) { … } uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, const char *func_name) { … } int amdgpu_dm_process_dmub_aux_transfer_sync( struct dc_context *ctx, unsigned int link_index, struct aux_payload *payload, enum aux_return_code_type *operation_result) { … } int amdgpu_dm_process_dmub_set_config_sync( struct dc_context *ctx, unsigned int link_index, struct set_config_cmd_payload *payload, enum set_config_status *operation_result) { … } bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) { … } bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) { … }
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