linux/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c

/*
 * Copyright 2012-15 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include "dcn20_mpc.h"

#include "reg_helper.h"
#include "dc.h"
#include "mem_input.h"
#include "dcn10/dcn10_cm_common.h"

#define REG(reg) …

#define IND_REG(index) …

#define CTX …

#undef FN
#define FN(reg_name, field_name) …

#define NUM_ELEMENTS(a) …

void mpc2_update_blending(
	struct mpc *mpc,
	struct mpcc_blnd_cfg *blnd_cfg,
	int mpcc_id)
{ … }

void mpc2_set_denorm(
		struct mpc *mpc,
		int opp_id,
		enum dc_color_depth output_depth)
{ … }

void mpc2_set_denorm_clamp(
		struct mpc *mpc,
		int opp_id,
		struct mpc_denorm_clamp denorm_clamp)
{ … }



void mpc2_set_output_csc(
		struct mpc *mpc,
		int opp_id,
		const uint16_t *regval,
		enum mpc_output_csc_mode ocsc_mode)
{ … }

void mpc2_set_ocsc_default(
		struct mpc *mpc,
		int opp_id,
		enum dc_color_space color_space,
		enum mpc_output_csc_mode ocsc_mode)
{ … }

static void mpc2_ogam_get_reg_field(
		struct mpc *mpc,
		struct xfer_func_reg *reg)
{ … }

void mpc20_power_on_ogam_lut(
		struct mpc *mpc, int mpcc_id,
		bool power_on)
{ … }

static void mpc20_configure_ogam_lut(
		struct mpc *mpc, int mpcc_id,
		bool is_ram_a)
{ … }

static enum dc_lut_mode mpc20_get_ogam_current(struct mpc *mpc, int mpcc_id)
{ … }

static void mpc2_program_lutb(struct mpc *mpc, int mpcc_id,
			const struct pwl_params *params)
{ … }

static void mpc2_program_luta(struct mpc *mpc, int mpcc_id,
		const struct pwl_params *params)
{ … }

static void mpc20_program_ogam_pwl(
		struct mpc *mpc, int mpcc_id,
		const struct pwl_result_data *rgb,
		uint32_t num)
{ … }

static void apply_DEDCN20_305_wa(struct mpc *mpc, int mpcc_id,
				 enum dc_lut_mode current_mode,
				 enum dc_lut_mode next_mode)
{ … }

void mpc2_set_output_gamma(
		struct mpc *mpc,
		int mpcc_id,
		const struct pwl_params *params)
{ … }
void mpc2_assert_idle_mpcc(struct mpc *mpc, int id)
{ … }

void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)
{ … }

static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
{ … }

static struct mpcc *mpc2_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id)
{ … }

static void mpc2_read_mpcc_state(
		struct mpc *mpc,
		int mpcc_inst,
		struct mpcc_state *s)
{ … }

static const struct mpc_funcs dcn20_mpc_funcs = …;

void dcn20_mpc_construct(struct dcn20_mpc *mpc20,
	struct dc_context *ctx,
	const struct dcn20_mpc_registers *mpc_regs,
	const struct dcn20_mpc_shift *mpc_shift,
	const struct dcn20_mpc_mask *mpc_mask,
	int num_mpcc)
{ … }