/* * Copyright 2012-15 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #include "dm_services.h" #include "dce/dce_12_0_offset.h" #include "dce/dce_12_0_sh_mask.h" #include "soc15_hw_ip.h" #include "vega10_ip_offset.h" #include "dc_types.h" #include "dc_bios_types.h" #include "include/grph_object_id.h" #include "include/logger_interface.h" #include "dce120_timing_generator.h" #include "timing_generator.h" #define CRTC_REG_UPDATE_N(reg_name, n, ...) … #define CRTC_REG_SET_N(reg_name, n, ...) … #define CRTC_REG_UPDATE(reg, field, val) … #define CRTC_REG_UPDATE_2(reg, field1, val1, field2, val2) … #define CRTC_REG_UPDATE_3(reg, field1, val1, field2, val2, field3, val3) … #define CRTC_REG_UPDATE_4(reg, field1, val1, field2, val2, field3, val3, field4, val4) … #define CRTC_REG_UPDATE_5(reg, field1, val1, field2, val2, field3, val3, field4, val4, field5, val5) … #define CRTC_REG_SET(reg, field, val) … #define CRTC_REG_SET_2(reg, field1, val1, field2, val2) … #define CRTC_REG_SET_3(reg, field1, val1, field2, val2, field3, val3) … /* ***************************************************************************** * Function: is_in_vertical_blank * * @brief * check the current status of CRTC to check if we are in Vertical Blank * regioneased" state * * @return * true if currently in blank region, false otherwise * ***************************************************************************** */ static bool dce120_timing_generator_is_in_vertical_blank( struct timing_generator *tg) { … } /* determine if given timing can be supported by TG */ static bool dce120_timing_generator_validate_timing( struct timing_generator *tg, const struct dc_crtc_timing *timing, enum signal_type signal) { … } static bool dce120_tg_validate_timing(struct timing_generator *tg, const struct dc_crtc_timing *timing) { … } /******** HW programming ************/ /* Disable/Enable Timing Generator */ static bool dce120_timing_generator_enable_crtc(struct timing_generator *tg) { … } static void dce120_timing_generator_set_early_control( struct timing_generator *tg, uint32_t early_cntl) { … } /**************** TG current status ******************/ /* return the current frame counter. Used by Linux kernel DRM */ static uint32_t dce120_timing_generator_get_vblank_counter( struct timing_generator *tg) { … } /* Get current H and V position */ static void dce120_timing_generator_get_crtc_position( struct timing_generator *tg, struct crtc_position *position) { … } /* wait until TG is in beginning of vertical blank region */ static void dce120_timing_generator_wait_for_vblank(struct timing_generator *tg) { … } /* wait until TG is in beginning of active region */ static void dce120_timing_generator_wait_for_vactive(struct timing_generator *tg) { … } /*********** Timing Generator Synchronization routines ****/ /* Setups Global Swap Lock group, TimingServer or TimingClient*/ static void dce120_timing_generator_setup_global_swap_lock( struct timing_generator *tg, const struct dcp_gsl_params *gsl_params) { … } /* Clear all the register writes done by setup_global_swap_lock */ static void dce120_timing_generator_tear_down_global_swap_lock( struct timing_generator *tg) { … } /* Reset slave controllers on master VSync */ static void dce120_timing_generator_enable_reset_trigger( struct timing_generator *tg, int source) { … } /* disabling trigger-reset */ static void dce120_timing_generator_disable_reset_trigger( struct timing_generator *tg) { … } /* Checks whether CRTC triggered reset occurred */ static bool dce120_timing_generator_did_triggered_reset_occur( struct timing_generator *tg) { … } /******** Stuff to move to other virtual HW objects *****************/ /* Move to enable accelerated mode */ static void dce120_timing_generator_disable_vga(struct timing_generator *tg) { … } /* TODO: Should we move it to transform */ /* Fully program CRTC timing in timing generator */ static void dce120_timing_generator_program_blanking( struct timing_generator *tg, const struct dc_crtc_timing *timing) { … } /* TODO: Should we move it to opp? */ /* Combine with below and move YUV/RGB color conversion to SW layer */ static void dce120_timing_generator_program_blank_color( struct timing_generator *tg, const struct tg_color *black_color) { … } /* Combine with above and move YUV/RGB color conversion to SW layer */ static void dce120_timing_generator_set_overscan_color_black( struct timing_generator *tg, const struct tg_color *color) { … } static void dce120_timing_generator_set_drr( struct timing_generator *tg, const struct drr_params *params) { … } static void dce120_timing_generator_get_crtc_scanoutpos( struct timing_generator *tg, uint32_t *v_blank_start, uint32_t *v_blank_end, uint32_t *h_position, uint32_t *v_position) { … } static void dce120_timing_generator_enable_advanced_request( struct timing_generator *tg, bool enable, const struct dc_crtc_timing *timing) { … } static void dce120_tg_program_blank_color(struct timing_generator *tg, const struct tg_color *black_color) { … } static void dce120_tg_set_overscan_color(struct timing_generator *tg, const struct tg_color *overscan_color) { … } static void dce120_tg_program_timing(struct timing_generator *tg, const struct dc_crtc_timing *timing, int vready_offset, int vstartup_start, int vupdate_offset, int vupdate_width, const enum signal_type signal, bool use_vbios) { … } static bool dce120_tg_is_blanked(struct timing_generator *tg) { … } static void dce120_tg_set_blank(struct timing_generator *tg, bool enable_blanking) { … } bool dce120_tg_validate_timing(struct timing_generator *tg, const struct dc_crtc_timing *timing); static void dce120_tg_wait_for_state(struct timing_generator *tg, enum crtc_state state) { … } static void dce120_tg_set_colors(struct timing_generator *tg, const struct tg_color *blank_color, const struct tg_color *overscan_color) { … } static void dce120_timing_generator_set_static_screen_control( struct timing_generator *tg, uint32_t event_triggers, uint32_t num_frames) { … } static void dce120_timing_generator_set_test_pattern( struct timing_generator *tg, /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode' * because this is not DP-specific (which is probably somewhere in DP * encoder) */ enum controller_dp_test_pattern test_pattern, enum dc_color_depth color_depth) { … } static bool dce120_arm_vert_intr( struct timing_generator *tg, uint8_t width) { … } static bool dce120_is_tg_enabled(struct timing_generator *tg) { … } static bool dce120_configure_crc(struct timing_generator *tg, const struct crc_params *params) { … } static bool dce120_get_crc(struct timing_generator *tg, uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) { … } static const struct timing_generator_funcs dce120_tg_funcs = …; void dce120_timing_generator_construct( struct dce110_timing_generator *tg110, struct dc_context *ctx, uint32_t instance, const struct dce110_timing_generator_offsets *offsets) { … }
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