linux/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

/*
 * Copyright 2020 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef _DMUB_DCN31_H_
#define _DMUB_DCN31_H_

#include "dmub_dcn20.h"

struct dmub_srv;

/* DCN31 register definitions. */

#define DMUB_DCN31_REGS() …

#define DMUB_DCN31_FIELDS() …

struct dmub_srv_dcn31_reg_offset { … };

struct dmub_srv_dcn31_reg_shift { … };

struct dmub_srv_dcn31_reg_mask { … };

struct dmub_srv_dcn31_regs { … };

extern const struct dmub_srv_dcn31_regs dmub_srv_dcn31_regs;

/* Hardware functions. */


void dmub_dcn31_init(struct dmub_srv *dmub);

void dmub_dcn31_reset(struct dmub_srv *dmub);

void dmub_dcn31_reset_release(struct dmub_srv *dmub);

void dmub_dcn31_backdoor_load(struct dmub_srv *dmub,
			      const struct dmub_window *cw0,
			      const struct dmub_window *cw1);

void dmub_dcn31_setup_windows(struct dmub_srv *dmub,
			      const struct dmub_window *cw2,
			      const struct dmub_window *cw3,
			      const struct dmub_window *cw4,
			      const struct dmub_window *cw5,
			      const struct dmub_window *cw6,
			      const struct dmub_window *region6);

void dmub_dcn31_setup_mailbox(struct dmub_srv *dmub,
			      const struct dmub_region *inbox1);

uint32_t dmub_dcn31_get_inbox1_wptr(struct dmub_srv *dmub);

uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub);

void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);

void dmub_dcn31_setup_out_mailbox(struct dmub_srv *dmub,
			      const struct dmub_region *outbox1);

uint32_t dmub_dcn31_get_outbox1_wptr(struct dmub_srv *dmub);

void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

bool dmub_dcn31_is_hw_init(struct dmub_srv *dmub);

bool dmub_dcn31_is_supported(struct dmub_srv *dmub);

bool dmub_dcn31_is_psrsu_supported(struct dmub_srv *dmub);

void dmub_dcn31_set_gpint(struct dmub_srv *dmub,
			  union dmub_gpint_data_register reg);

bool dmub_dcn31_is_gpint_acked(struct dmub_srv *dmub,
			       union dmub_gpint_data_register reg);

uint32_t dmub_dcn31_get_gpint_response(struct dmub_srv *dmub);

uint32_t dmub_dcn31_get_gpint_dataout(struct dmub_srv *dmub);

void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);

void dmub_dcn31_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);

union dmub_fw_boot_status dmub_dcn31_get_fw_boot_status(struct dmub_srv *dmub);

union dmub_fw_boot_options dmub_dcn31_get_fw_boot_option(struct dmub_srv *dmub);

void dmub_dcn31_setup_outbox0(struct dmub_srv *dmub,
			      const struct dmub_region *outbox0);

uint32_t dmub_dcn31_get_outbox0_wptr(struct dmub_srv *dmub);

void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub);

void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data);

bool dmub_dcn31_should_detect(struct dmub_srv *dmub);

#endif /* _DMUB_DCN31_H_ */