// SPDX-License-Identifier: GPL-2.0 /* * Renesas RZ/G2L IRQC Driver * * Copyright (C) 2022 Renesas Electronics Corporation. * * Author: Lad Prabhakar <[email protected]> */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/err.h> #include <linux/io.h> #include <linux/irqchip.h> #include <linux/irqdomain.h> #include <linux/of_address.h> #include <linux/of_platform.h> #include <linux/pm_runtime.h> #include <linux/reset.h> #include <linux/spinlock.h> #include <linux/syscore_ops.h> #define IRQC_IRQ_START … #define IRQC_IRQ_COUNT … #define IRQC_TINT_START … #define IRQC_TINT_COUNT … #define IRQC_NUM_IRQ … #define ISCR … #define IITSR … #define TSCR … #define TITSR(n) … #define TITSR0_MAX_INT … #define TITSEL_WIDTH … #define TSSR(n) … #define TIEN … #define TSSEL_SHIFT(n) … #define TSSEL_MASK … #define IRQ_MASK … #define IMSK … #define TMSK … #define TSSR_OFFSET(n) … #define TSSR_INDEX(n) … #define TITSR_TITSEL_EDGE_RISING … #define TITSR_TITSEL_EDGE_FALLING … #define TITSR_TITSEL_LEVEL_HIGH … #define TITSR_TITSEL_LEVEL_LOW … #define IITSR_IITSEL(n, sense) … #define IITSR_IITSEL_LEVEL_LOW … #define IITSR_IITSEL_EDGE_FALLING … #define IITSR_IITSEL_EDGE_RISING … #define IITSR_IITSEL_EDGE_BOTH … #define IITSR_IITSEL_MASK(n) … #define TINT_EXTRACT_HWIRQ(x) … #define TINT_EXTRACT_GPIOINT(x) … /** * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/resume) * @iitsr: IITSR register * @titsr: TITSR registers */ struct rzg2l_irqc_reg_cache { … }; /** * struct rzg2l_irqc_priv - IRQ controller private data structure * @base: Controller's base address * @irqchip: Pointer to struct irq_chip * @fwspec: IRQ firmware specific data * @lock: Lock to serialize access to hardware registers * @cache: Registers cache for suspend/resume */ static struct rzg2l_irqc_priv { … } *rzg2l_irqc_data; static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data) { … } static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq) { … } static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq) { … } static void rzg2l_irqc_eoi(struct irq_data *d) { … } static void rzfive_irqc_mask_irq_interrupt(struct rzg2l_irqc_priv *priv, unsigned int hwirq) { … } static void rzfive_irqc_unmask_irq_interrupt(struct rzg2l_irqc_priv *priv, unsigned int hwirq) { … } static void rzfive_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv, unsigned int hwirq) { … } static void rzfive_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *priv, unsigned int hwirq) { … } static void rzfive_irqc_mask(struct irq_data *d) { … } static void rzfive_irqc_unmask(struct irq_data *d) { … } static void rzfive_tint_irq_endisable(struct irq_data *d, bool enable) { … } static void rzfive_irqc_irq_disable(struct irq_data *d) { … } static void rzfive_irqc_irq_enable(struct irq_data *d) { … } static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable) { … } static void rzg2l_irqc_irq_disable(struct irq_data *d) { … } static void rzg2l_irqc_irq_enable(struct irq_data *d) { … } static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) { … } static u32 rzg2l_disable_tint_and_set_tint_source(struct irq_data *d, struct rzg2l_irqc_priv *priv, u32 reg, u32 tssr_offset, u8 tssr_index) { … } static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) { … } static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type) { … } static int rzg2l_irqc_irq_suspend(void) { … } static void rzg2l_irqc_irq_resume(void) { … } static struct syscore_ops rzg2l_irqc_syscore_ops = …; static const struct irq_chip rzg2l_irqc_chip = …; static const struct irq_chip rzfive_irqc_chip = …; static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, void *arg) { … } static const struct irq_domain_ops rzg2l_irqc_domain_ops = …; static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv, struct device_node *np) { … } static int rzg2l_irqc_common_init(struct device_node *node, struct device_node *parent, const struct irq_chip *irq_chip) { … } static int __init rzg2l_irqc_init(struct device_node *node, struct device_node *parent) { … } static int __init rzfive_irqc_init(struct device_node *node, struct device_node *parent) { … } IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc) IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init) IRQCHIP_MATCH("renesas,r9a07g043f-irqc", rzfive_irqc_init) IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc) MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …;
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