linux/drivers/irqchip/irq-imx-mu-msi.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Freescale MU used as MSI controller
 *
 * Copyright (c) 2018 Pengutronix, Oleksij Rempel <[email protected]>
 * Copyright 2022 NXP
 *	Frank Li <[email protected]>
 *	Peng Fan <[email protected]>
 *
 * Based on drivers/mailbox/imx-mailbox.c
 */

#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/msi.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <linux/pm_domain.h>
#include <linux/spinlock.h>

#include "irq-msi-lib.h"

#define IMX_MU_CHANS …

enum imx_mu_xcr { … };

enum imx_mu_xsr { … };

enum imx_mu_type { … };

/* Receive Interrupt Enable */
#define IMX_MU_xCR_RIEn(data, x) …
#define IMX_MU_xSR_RFn(data, x) …

struct imx_mu_dcfg { … };

struct imx_mu_msi { … };

static void imx_mu_write(struct imx_mu_msi *msi_data, u32 val, u32 offs)
{ … }

static u32 imx_mu_read(struct imx_mu_msi *msi_data, u32 offs)
{ … }

static u32 imx_mu_xcr_rmw(struct imx_mu_msi *msi_data, enum imx_mu_xcr type, u32 set, u32 clr)
{ … }

static void imx_mu_msi_parent_mask_irq(struct irq_data *data)
{ … }

static void imx_mu_msi_parent_unmask_irq(struct irq_data *data)
{ … }

static void imx_mu_msi_parent_ack_irq(struct irq_data *data)
{ … }

static void imx_mu_msi_parent_compose_msg(struct irq_data *data,
					  struct msi_msg *msg)
{ … }

static int imx_mu_msi_parent_set_affinity(struct irq_data *irq_data,
				   const struct cpumask *mask, bool force)
{ … }

static struct irq_chip imx_mu_msi_parent_chip = …;

static int imx_mu_msi_domain_irq_alloc(struct irq_domain *domain,
					unsigned int virq,
					unsigned int nr_irqs,
					void *args)
{ … }

static void imx_mu_msi_domain_irq_free(struct irq_domain *domain,
				       unsigned int virq, unsigned int nr_irqs)
{ … }

static const struct irq_domain_ops imx_mu_msi_domain_ops = …;

static void imx_mu_msi_irq_handler(struct irq_desc *desc)
{ … }

#define IMX_MU_MSI_FLAGS_REQUIRED …

#define IMX_MU_MSI_FLAGS_SUPPORTED …

static const struct msi_parent_ops imx_mu_msi_parent_ops = …;

static int imx_mu_msi_domains_init(struct imx_mu_msi *msi_data, struct device *dev)
{ … }

/* Register offset of different version MU IP */
static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = …;

static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = …;

static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = …;

static int __init imx_mu_of_init(struct device_node *dn,
				 struct device_node *parent,
				 const struct imx_mu_dcfg *cfg)
{ … }

static int __maybe_unused imx_mu_runtime_suspend(struct device *dev)
{ … }

static int __maybe_unused imx_mu_runtime_resume(struct device *dev)
{ … }

static const struct dev_pm_ops imx_mu_pm_ops = …;

static int __init imx_mu_imx7ulp_of_init(struct device_node *dn,
					 struct device_node *parent)
{ … }

static int __init imx_mu_imx6sx_of_init(struct device_node *dn,
					struct device_node *parent)
{ … }

static int __init imx_mu_imx8ulp_of_init(struct device_node *dn,
					 struct device_node *parent)
{ … }

IRQCHIP_PLATFORM_DRIVER_BEGIN(imx_mu_msi)
IRQCHIP_MATCH("fsl,imx7ulp-mu-msi", imx_mu_imx7ulp_of_init)
IRQCHIP_MATCH("fsl,imx6sx-mu-msi", imx_mu_imx6sx_of_init)
IRQCHIP_MATCH("fsl,imx8ulp-mu-msi", imx_mu_imx8ulp_of_init)
IRQCHIP_PLATFORM_DRIVER_END(imx_mu_msi, .pm = …


MODULE_AUTHOR(…) …;
MODULE_DESCRIPTION(…) …;
MODULE_LICENSE(…) …;