// SPDX-License-Identifier: GPL-2.0 /* * Meson AXG MIPI DPHY driver * * Copyright (C) 2018 Amlogic, Inc. All rights reserved * Copyright (C) 2020 BayLibre, SAS * Author: Neil Armstrong <[email protected]> */ #include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/bits.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/regmap.h> #include <linux/reset.h> #include <linux/phy/phy.h> #include <linux/platform_device.h> /* [31] soft reset for the phy. * 1: reset. 0: dessert the reset. * [30] clock lane soft reset. * [29] data byte lane 3 soft reset. * [28] data byte lane 2 soft reset. * [27] data byte lane 1 soft reset. * [26] data byte lane 0 soft reset. * [25] mipi dsi pll clock selection. * 1: clock from fixed 850Mhz clock source. 0: from VID2 PLL. * [12] mipi HSbyteclk enable. * [11] mipi divider clk selection. * 1: select the mipi DDRCLKHS from clock divider. * 0: from PLL clock. * [10] mipi clock divider control. * 1: /4. 0: /2. * [9] mipi divider output enable. * [8] mipi divider counter enable. * [7] PLL clock enable. * [5] LPDT data endian. * 1 = transfer the high bit first. 0 : transfer the low bit first. * [4] HS data endian. * [3] force data byte lane in stop mode. * [2] force data byte lane 0 in receiver mode. * [1] write 1 to sync the txclkesc input. the internal logic have to * use txclkesc to decide Txvalid and Txready. * [0] enalbe the MIPI DPHY TxDDRClk. */ #define MIPI_DSI_PHY_CTRL … /* [31] clk lane tx_hs_en control selection. * 1: from register. 0: use clk lane state machine. * [30] register bit for clock lane tx_hs_en. * [29] clk lane tx_lp_en contrl selection. * 1: from register. 0: from clk lane state machine. * [28] register bit for clock lane tx_lp_en. * [27] chan0 tx_hs_en control selection. * 1: from register. 0: from chan0 state machine. * [26] register bit for chan0 tx_hs_en. * [25] chan0 tx_lp_en control selection. * 1: from register. 0: from chan0 state machine. * [24] register bit from chan0 tx_lp_en. * [23] chan0 rx_lp_en control selection. * 1: from register. 0: from chan0 state machine. * [22] register bit from chan0 rx_lp_en. * [21] chan0 contention detection enable control selection. * 1: from register. 0: from chan0 state machine. * [20] register bit from chan0 contention dectection enable. * [19] chan1 tx_hs_en control selection. * 1: from register. 0: from chan0 state machine. * [18] register bit for chan1 tx_hs_en. * [17] chan1 tx_lp_en control selection. * 1: from register. 0: from chan0 state machine. * [16] register bit from chan1 tx_lp_en. * [15] chan2 tx_hs_en control selection. * 1: from register. 0: from chan0 state machine. * [14] register bit for chan2 tx_hs_en. * [13] chan2 tx_lp_en control selection. * 1: from register. 0: from chan0 state machine. * [12] register bit from chan2 tx_lp_en. * [11] chan3 tx_hs_en control selection. * 1: from register. 0: from chan0 state machine. * [10] register bit for chan3 tx_hs_en. * [9] chan3 tx_lp_en control selection. * 1: from register. 0: from chan0 state machine. * [8] register bit from chan3 tx_lp_en. * [4] clk chan power down. this bit is also used as the power down * of the whole MIPI_DSI_PHY. * [3] chan3 power down. * [2] chan2 power down. * [1] chan1 power down. * [0] chan0 power down. */ #define MIPI_DSI_CHAN_CTRL … /* [24] rx turn watch dog triggered. * [23] rx esc watchdog triggered. * [22] mbias ready. * [21] txclkesc synced and ready. * [20:17] clk lane state. {mbias_ready, tx_stop, tx_ulps, tx_hs_active} * [16:13] chan3 state{0, tx_stop, tx_ulps, tx_hs_active} * [12:9] chan2 state.{0, tx_stop, tx_ulps, tx_hs_active} * [8:5] chan1 state. {0, tx_stop, tx_ulps, tx_hs_active} * [4:0] chan0 state. {TX_STOP, tx_ULPS, hs_active, direction, rxulpsesc} */ #define MIPI_DSI_CHAN_STS … /* [31:24] TCLK_PREPARE. * [23:16] TCLK_ZERO. * [15:8] TCLK_POST. * [7:0] TCLK_TRAIL. */ #define MIPI_DSI_CLK_TIM … /* [31:24] THS_PREPARE. * [23:16] THS_ZERO. * [15:8] THS_TRAIL. * [7:0] THS_EXIT. */ #define MIPI_DSI_HS_TIM … /* [31:24] tTA_GET. * [23:16] tTA_GO. * [15:8] tTA_SURE. * [7:0] tLPX. */ #define MIPI_DSI_LP_TIM … /* wait time to MIPI DIS analog ready. */ #define MIPI_DSI_ANA_UP_TIM … /* TINIT. */ #define MIPI_DSI_INIT_TIM … /* TWAKEUP. */ #define MIPI_DSI_WAKEUP_TIM … /* when in RxULPS check state, after the logic enable the analog, * how long we should wait to check the lP state . */ #define MIPI_DSI_LPOK_TIM … /* Watchdog for RX low power state no finished. */ #define MIPI_DSI_LP_WCHDOG … /* tMBIAS, after send power up signals to analog, * how long we should wait for analog powered up. */ #define MIPI_DSI_ANA_CTRL … /* [31:8] reserved for future. * [7:0] tCLK_PRE. */ #define MIPI_DSI_CLK_TIM1 … /* watchdog for turn around waiting time. */ #define MIPI_DSI_TURN_WCHDOG … /* When in RxULPS state, how frequency we should to check * if the TX side out of ULPS state. */ #define MIPI_DSI_ULPS_CHECK … #define MIPI_DSI_TEST_CTRL0 … #define MIPI_DSI_TEST_CTRL1 … struct phy_meson_axg_mipi_dphy_priv { … }; static const struct regmap_config phy_meson_axg_mipi_dphy_regmap_conf = …; static int phy_meson_axg_mipi_dphy_init(struct phy *phy) { … } static int phy_meson_axg_mipi_dphy_configure(struct phy *phy, union phy_configure_opts *opts) { … } static int phy_meson_axg_mipi_dphy_power_on(struct phy *phy) { … } static int phy_meson_axg_mipi_dphy_power_off(struct phy *phy) { … } static int phy_meson_axg_mipi_dphy_exit(struct phy *phy) { … } static const struct phy_ops phy_meson_axg_mipi_dphy_ops = …; static int phy_meson_axg_mipi_dphy_probe(struct platform_device *pdev) { … } static const struct of_device_id phy_meson_axg_mipi_dphy_of_match[] = …; MODULE_DEVICE_TABLE(of, phy_meson_axg_mipi_dphy_of_match); static struct platform_driver phy_meson_axg_mipi_dphy_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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