/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * linux/mdio.h: definitions for MDIO (clause 45) transceivers * Copyright 2006-2009 Solarflare Communications Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published * by the Free Software Foundation, incorporated herein by reference. */ #ifndef _UAPI__LINUX_MDIO_H__ #define _UAPI__LINUX_MDIO_H__ #include <linux/types.h> #include <linux/mii.h> /* MDIO Manageable Devices (MMDs). */ #define MDIO_MMD_PMAPMD … #define MDIO_MMD_WIS … #define MDIO_MMD_PCS … #define MDIO_MMD_PHYXS … #define MDIO_MMD_DTEXS … #define MDIO_MMD_TC … #define MDIO_MMD_AN … #define MDIO_MMD_C22EXT … #define MDIO_MMD_VEND1 … #define MDIO_MMD_VEND2 … /* Generic MDIO registers. */ #define MDIO_CTRL1 … #define MDIO_STAT1 … #define MDIO_DEVID1 … #define MDIO_DEVID2 … #define MDIO_SPEED … #define MDIO_DEVS1 … #define MDIO_DEVS2 … #define MDIO_CTRL2 … #define MDIO_STAT2 … #define MDIO_PMA_TXDIS … #define MDIO_PMA_RXDET … #define MDIO_PMA_EXTABLE … #define MDIO_PKGID1 … #define MDIO_PKGID2 … #define MDIO_AN_ADVERTISE … #define MDIO_AN_LPA … #define MDIO_PCS_EEE_ABLE … #define MDIO_PCS_EEE_ABLE2 … #define MDIO_PMA_NG_EXTABLE … #define MDIO_PCS_EEE_WK_ERR … #define MDIO_PHYXS_LNSTAT … #define MDIO_AN_EEE_ADV … #define MDIO_AN_EEE_LPABLE … #define MDIO_AN_EEE_ADV2 … #define MDIO_AN_EEE_LPABLE2 … #define MDIO_AN_CTRL2 … /* Media-dependent registers. */ #define MDIO_PMA_10GBT_SWAPPOL … #define MDIO_PMA_10GBT_TXPWR … #define MDIO_PMA_10GBT_SNR … #define MDIO_PMA_10GBR_FSRT_CSR … #define MDIO_PMA_10GBR_FECABLE … #define MDIO_PCS_10GBX_STAT1 … #define MDIO_PCS_10GBRT_STAT1 … #define MDIO_PCS_10GBRT_STAT2 … #define MDIO_AN_10GBT_CTRL … #define MDIO_AN_10GBT_STAT … #define MDIO_B10L_PMA_CTRL … #define MDIO_PMA_10T1L_STAT … #define MDIO_PCS_10T1L_CTRL … #define MDIO_PMA_PMD_BT1 … #define MDIO_AN_T1_CTRL … #define MDIO_AN_T1_STAT … #define MDIO_AN_T1_ADV_L … #define MDIO_AN_T1_ADV_M … #define MDIO_AN_T1_ADV_H … #define MDIO_AN_T1_LP_L … #define MDIO_AN_T1_LP_M … #define MDIO_AN_T1_LP_H … #define MDIO_AN_10BT1_AN_CTRL … #define MDIO_AN_10BT1_AN_STAT … #define MDIO_PMA_PMD_BT1_CTRL … #define MDIO_PCS_1000BT1_CTRL … #define MDIO_PCS_1000BT1_STAT … /* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */ #define MDIO_PMA_LASI_RXCTRL … #define MDIO_PMA_LASI_TXCTRL … #define MDIO_PMA_LASI_CTRL … #define MDIO_PMA_LASI_RXSTAT … #define MDIO_PMA_LASI_TXSTAT … #define MDIO_PMA_LASI_STAT … /* Control register 1. */ /* Enable extended speed selection */ #define MDIO_CTRL1_SPEEDSELEXT … /* All speed selection bits */ #define MDIO_CTRL1_SPEEDSEL … #define MDIO_CTRL1_FULLDPLX … #define MDIO_CTRL1_LPOWER … #define MDIO_CTRL1_RESET … #define MDIO_PMA_CTRL1_LOOPBACK … #define MDIO_PMA_CTRL1_SPEED1000 … #define MDIO_PMA_CTRL1_SPEED100 … #define MDIO_PCS_CTRL1_LOOPBACK … #define MDIO_PHYXS_CTRL1_LOOPBACK … #define MDIO_AN_CTRL1_RESTART … #define MDIO_AN_CTRL1_ENABLE … #define MDIO_AN_CTRL1_XNP … #define MDIO_PCS_CTRL1_CLKSTOP_EN … /* 10 Gb/s */ #define MDIO_CTRL1_SPEED10G … /* 10PASS-TS/2BASE-TL */ #define MDIO_CTRL1_SPEED10P2B … /* 2.5 Gb/s */ #define MDIO_CTRL1_SPEED2_5G … /* 5 Gb/s */ #define MDIO_CTRL1_SPEED5G … /* Status register 1. */ #define MDIO_STAT1_LPOWERABLE … #define MDIO_STAT1_LSTATUS … #define MDIO_STAT1_FAULT … #define MDIO_AN_STAT1_LPABLE … #define MDIO_AN_STAT1_ABLE … #define MDIO_AN_STAT1_RFAULT … #define MDIO_AN_STAT1_COMPLETE … #define MDIO_AN_STAT1_PAGE … #define MDIO_AN_STAT1_XNP … /* Speed register. */ #define MDIO_SPEED_10G … #define MDIO_PMA_SPEED_2B … #define MDIO_PMA_SPEED_10P … #define MDIO_PMA_SPEED_1000 … #define MDIO_PMA_SPEED_100 … #define MDIO_PMA_SPEED_10 … #define MDIO_PMA_SPEED_2_5G … #define MDIO_PMA_SPEED_5G … #define MDIO_PCS_SPEED_10P2B … #define MDIO_PCS_SPEED_2_5G … #define MDIO_PCS_SPEED_5G … /* Device present registers. */ #define MDIO_DEVS_PRESENT(devad) … #define MDIO_DEVS_C22PRESENT … #define MDIO_DEVS_PMAPMD … #define MDIO_DEVS_WIS … #define MDIO_DEVS_PCS … #define MDIO_DEVS_PHYXS … #define MDIO_DEVS_DTEXS … #define MDIO_DEVS_TC … #define MDIO_DEVS_AN … #define MDIO_DEVS_C22EXT … #define MDIO_DEVS_VEND1 … #define MDIO_DEVS_VEND2 … /* Control register 2. */ #define MDIO_PMA_CTRL2_TYPE … #define MDIO_PMA_CTRL2_10GBCX4 … #define MDIO_PMA_CTRL2_10GBEW … #define MDIO_PMA_CTRL2_10GBLW … #define MDIO_PMA_CTRL2_10GBSW … #define MDIO_PMA_CTRL2_10GBLX4 … #define MDIO_PMA_CTRL2_10GBER … #define MDIO_PMA_CTRL2_10GBLR … #define MDIO_PMA_CTRL2_10GBSR … #define MDIO_PMA_CTRL2_10GBLRM … #define MDIO_PMA_CTRL2_10GBT … #define MDIO_PMA_CTRL2_10GBKX4 … #define MDIO_PMA_CTRL2_10GBKR … #define MDIO_PMA_CTRL2_1000BT … #define MDIO_PMA_CTRL2_1000BKX … #define MDIO_PMA_CTRL2_100BTX … #define MDIO_PMA_CTRL2_10BT … #define MDIO_PMA_CTRL2_2_5GBT … #define MDIO_PMA_CTRL2_5GBT … #define MDIO_PMA_CTRL2_BASET1 … #define MDIO_PCS_CTRL2_TYPE … #define MDIO_PCS_CTRL2_10GBR … #define MDIO_PCS_CTRL2_10GBX … #define MDIO_PCS_CTRL2_10GBW … #define MDIO_PCS_CTRL2_10GBT … /* Status register 2. */ #define MDIO_STAT2_RXFAULT … #define MDIO_STAT2_TXFAULT … #define MDIO_STAT2_DEVPRST … #define MDIO_STAT2_DEVPRST_VAL … #define MDIO_PMA_STAT2_LBABLE … #define MDIO_PMA_STAT2_10GBEW … #define MDIO_PMA_STAT2_10GBLW … #define MDIO_PMA_STAT2_10GBSW … #define MDIO_PMA_STAT2_10GBLX4 … #define MDIO_PMA_STAT2_10GBER … #define MDIO_PMA_STAT2_10GBLR … #define MDIO_PMA_STAT2_10GBSR … #define MDIO_PMD_STAT2_TXDISAB … #define MDIO_PMA_STAT2_EXTABLE … #define MDIO_PMA_STAT2_RXFLTABLE … #define MDIO_PMA_STAT2_TXFLTABLE … #define MDIO_PCS_STAT2_10GBR … #define MDIO_PCS_STAT2_10GBX … #define MDIO_PCS_STAT2_10GBW … #define MDIO_PCS_STAT2_RXFLTABLE … #define MDIO_PCS_STAT2_TXFLTABLE … /* Transmit disable register. */ #define MDIO_PMD_TXDIS_GLOBAL … #define MDIO_PMD_TXDIS_0 … #define MDIO_PMD_TXDIS_1 … #define MDIO_PMD_TXDIS_2 … #define MDIO_PMD_TXDIS_3 … /* Receive signal detect register. */ #define MDIO_PMD_RXDET_GLOBAL … #define MDIO_PMD_RXDET_0 … #define MDIO_PMD_RXDET_1 … #define MDIO_PMD_RXDET_2 … #define MDIO_PMD_RXDET_3 … /* Extended abilities register. */ #define MDIO_PMA_EXTABLE_10GCX4 … #define MDIO_PMA_EXTABLE_10GBLRM … #define MDIO_PMA_EXTABLE_10GBT … #define MDIO_PMA_EXTABLE_10GBKX4 … #define MDIO_PMA_EXTABLE_10GBKR … #define MDIO_PMA_EXTABLE_1000BT … #define MDIO_PMA_EXTABLE_1000BKX … #define MDIO_PMA_EXTABLE_100BTX … #define MDIO_PMA_EXTABLE_10BT … #define MDIO_PMA_EXTABLE_BT1 … #define MDIO_PMA_EXTABLE_NBT … /* AN Clause 73 linkword */ #define MDIO_AN_C73_0_S_MASK … #define MDIO_AN_C73_0_E_MASK … #define MDIO_AN_C73_0_PAUSE … #define MDIO_AN_C73_0_ASM_DIR … #define MDIO_AN_C73_0_C2 … #define MDIO_AN_C73_0_RF … #define MDIO_AN_C73_0_ACK … #define MDIO_AN_C73_0_NP … #define MDIO_AN_C73_1_T_MASK … #define MDIO_AN_C73_1_1000BASE_KX … #define MDIO_AN_C73_1_10GBASE_KX4 … #define MDIO_AN_C73_1_10GBASE_KR … #define MDIO_AN_C73_1_40GBASE_KR4 … #define MDIO_AN_C73_1_40GBASE_CR4 … #define MDIO_AN_C73_1_100GBASE_CR10 … #define MDIO_AN_C73_1_100GBASE_KP4 … #define MDIO_AN_C73_1_100GBASE_KR4 … #define MDIO_AN_C73_1_100GBASE_CR4 … #define MDIO_AN_C73_1_25GBASE_R_S … #define MDIO_AN_C73_1_25GBASE_R … #define MDIO_AN_C73_2_2500BASE_KX … #define MDIO_AN_C73_2_5GBASE_KR … /* PHY XGXS lane state register. */ #define MDIO_PHYXS_LNSTAT_SYNC0 … #define MDIO_PHYXS_LNSTAT_SYNC1 … #define MDIO_PHYXS_LNSTAT_SYNC2 … #define MDIO_PHYXS_LNSTAT_SYNC3 … #define MDIO_PHYXS_LNSTAT_ALIGN … /* PMA 10GBASE-T pair swap & polarity */ #define MDIO_PMA_10GBT_SWAPPOL_ABNX … #define MDIO_PMA_10GBT_SWAPPOL_CDNX … #define MDIO_PMA_10GBT_SWAPPOL_AREV … #define MDIO_PMA_10GBT_SWAPPOL_BREV … #define MDIO_PMA_10GBT_SWAPPOL_CREV … #define MDIO_PMA_10GBT_SWAPPOL_DREV … /* PMA 10GBASE-T TX power register. */ #define MDIO_PMA_10GBT_TXPWR_SHORT … /* PMA 10GBASE-T SNR registers. */ /* Value is SNR margin in dB, clamped to range [-127, 127], plus 0x8000. */ #define MDIO_PMA_10GBT_SNR_BIAS … #define MDIO_PMA_10GBT_SNR_MAX … /* PMA 10GBASE-R FEC ability register. */ #define MDIO_PMA_10GBR_FECABLE_ABLE … #define MDIO_PMA_10GBR_FECABLE_ERRABLE … /* PMA 10GBASE-R Fast Retrain status and control register. */ #define MDIO_PMA_10GBR_FSRT_ENABLE … /* PCS 10GBASE-R/-T status register 1. */ #define MDIO_PCS_10GBRT_STAT1_BLKLK … /* PCS 10GBASE-R/-T status register 2. */ #define MDIO_PCS_10GBRT_STAT2_ERR … #define MDIO_PCS_10GBRT_STAT2_BER … /* AN 10GBASE-T control register. */ #define MDIO_AN_10GBT_CTRL_ADVFSRT2_5G … #define MDIO_AN_10GBT_CTRL_ADV2_5G … #define MDIO_AN_10GBT_CTRL_ADV5G … #define MDIO_AN_10GBT_CTRL_ADV10G … /* AN 10GBASE-T status register. */ #define MDIO_AN_10GBT_STAT_LP2_5G … #define MDIO_AN_10GBT_STAT_LP5G … #define MDIO_AN_10GBT_STAT_LPTRR … #define MDIO_AN_10GBT_STAT_LPLTABLE … #define MDIO_AN_10GBT_STAT_LP10G … #define MDIO_AN_10GBT_STAT_REMOK … #define MDIO_AN_10GBT_STAT_LOCOK … #define MDIO_AN_10GBT_STAT_MS … #define MDIO_AN_10GBT_STAT_MSFLT … /* 10BASE-T1L PMA control */ #define MDIO_PMA_10T1L_CTRL_LB_EN … #define MDIO_PMA_10T1L_CTRL_EEE_EN … #define MDIO_PMA_10T1L_CTRL_LOW_POWER … #define MDIO_PMA_10T1L_CTRL_2V4_EN … #define MDIO_PMA_10T1L_CTRL_TX_DIS … #define MDIO_PMA_10T1L_CTRL_PMA_RST … /* 10BASE-T1L PMA status register. */ #define MDIO_PMA_10T1L_STAT_LINK … #define MDIO_PMA_10T1L_STAT_FAULT … #define MDIO_PMA_10T1L_STAT_POLARITY … #define MDIO_PMA_10T1L_STAT_RECV_FAULT … #define MDIO_PMA_10T1L_STAT_EEE … #define MDIO_PMA_10T1L_STAT_LOW_POWER … #define MDIO_PMA_10T1L_STAT_2V4_ABLE … #define MDIO_PMA_10T1L_STAT_LB_ABLE … /* 10BASE-T1L PCS control register. */ #define MDIO_PCS_10T1L_CTRL_LB … #define MDIO_PCS_10T1L_CTRL_RESET … /* BASE-T1 PMA/PMD extended ability register. */ #define MDIO_PMA_PMD_BT1_B100_ABLE … #define MDIO_PMA_PMD_BT1_B1000_ABLE … #define MDIO_PMA_PMD_BT1_B10L_ABLE … /* BASE-T1 auto-negotiation advertisement register [15:0] */ #define MDIO_AN_T1_ADV_L_PAUSE_CAP … #define MDIO_AN_T1_ADV_L_PAUSE_ASYM … #define MDIO_AN_T1_ADV_L_FORCE_MS … #define MDIO_AN_T1_ADV_L_REMOTE_FAULT … #define MDIO_AN_T1_ADV_L_ACK … #define MDIO_AN_T1_ADV_L_NEXT_PAGE_REQ … /* BASE-T1 auto-negotiation advertisement register [31:16] */ #define MDIO_AN_T1_ADV_M_B10L … #define MDIO_AN_T1_ADV_M_1000BT1 … #define MDIO_AN_T1_ADV_M_100BT1 … #define MDIO_AN_T1_ADV_M_MST … /* BASE-T1 auto-negotiation advertisement register [47:32] */ #define MDIO_AN_T1_ADV_H_10L_TX_HI_REQ … #define MDIO_AN_T1_ADV_H_10L_TX_HI … /* BASE-T1 AN LP Base Page ability register [15:0] */ #define MDIO_AN_T1_LP_L_PAUSE_CAP … #define MDIO_AN_T1_LP_L_PAUSE_ASYM … #define MDIO_AN_T1_LP_L_FORCE_MS … #define MDIO_AN_T1_LP_L_REMOTE_FAULT … #define MDIO_AN_T1_LP_L_ACK … #define MDIO_AN_T1_LP_L_NEXT_PAGE_REQ … /* BASE-T1 AN LP Base Page ability register [31:16] */ #define MDIO_AN_T1_LP_M_MST … #define MDIO_AN_T1_LP_M_B10L … /* BASE-T1 AN LP Base Page ability register [47:32] */ #define MDIO_AN_T1_LP_H_10L_TX_HI_REQ … #define MDIO_AN_T1_LP_H_10L_TX_HI … /* 10BASE-T1 AN control register */ #define MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L … /* 10BASE-T1 AN status register */ #define MDIO_AN_10BT1_AN_STAT_LPA_EEE_T1L … /* BASE-T1 PMA/PMD control register */ #define MDIO_PMA_PMD_BT1_CTRL_STRAP … #define MDIO_PMA_PMD_BT1_CTRL_STRAP_B1000 … #define MDIO_PMA_PMD_BT1_CTRL_CFG_MST … /* 1000BASE-T1 PCS control register */ #define MDIO_PCS_1000BT1_CTRL_LOW_POWER … #define MDIO_PCS_1000BT1_CTRL_DISABLE_TX … #define MDIO_PCS_1000BT1_CTRL_RESET … /* 1000BASE-T1 PCS status register */ #define MDIO_PCS_1000BT1_STAT_LINK … #define MDIO_PCS_1000BT1_STAT_FAULT … /* EEE Supported/Advertisement/LP Advertisement registers. * * EEE capability Register (3.20), Advertisement (7.60) and * Link partner ability (7.61) registers have and can use the same identical * bit masks. */ #define MDIO_AN_EEE_ADV_100TX … #define MDIO_AN_EEE_ADV_1000T … /* Note: the two defines above can be potentially used by the user-land * and cannot remove them now. * So, we define the new generic MDIO_EEE_100TX and MDIO_EEE_1000T macros * using the previous ones (that can be considered obsolete). */ #define MDIO_EEE_100TX … #define MDIO_EEE_1000T … #define MDIO_EEE_10GT … #define MDIO_EEE_1000KX … #define MDIO_EEE_10GKX4 … #define MDIO_EEE_10GKR … #define MDIO_EEE_40GR_FW … #define MDIO_EEE_40GR_DS … #define MDIO_EEE_100GR_FW … #define MDIO_EEE_100GR_DS … #define MDIO_EEE_2_5GT … #define MDIO_EEE_5GT … /* AN MultiGBASE-T AN control 2 */ #define MDIO_AN_THP_BP2_5GT … /* 2.5G/5G Extended abilities register. */ #define MDIO_PMA_NG_EXTABLE_2_5GBT … #define MDIO_PMA_NG_EXTABLE_5GBT … /* LASI RX_ALARM control/status registers. */ #define MDIO_PMA_LASI_RX_PHYXSLFLT … #define MDIO_PMA_LASI_RX_PCSLFLT … #define MDIO_PMA_LASI_RX_PMALFLT … #define MDIO_PMA_LASI_RX_OPTICPOWERFLT … #define MDIO_PMA_LASI_RX_WISLFLT … /* LASI TX_ALARM control/status registers. */ #define MDIO_PMA_LASI_TX_PHYXSLFLT … #define MDIO_PMA_LASI_TX_PCSLFLT … #define MDIO_PMA_LASI_TX_PMALFLT … #define MDIO_PMA_LASI_TX_LASERPOWERFLT … #define MDIO_PMA_LASI_TX_LASERTEMPFLT … #define MDIO_PMA_LASI_TX_LASERBICURRFLT … /* LASI control/status registers. */ #define MDIO_PMA_LASI_LSALARM … #define MDIO_PMA_LASI_TXALARM … #define MDIO_PMA_LASI_RXALARM … /* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */ #define MDIO_PHY_ID_C45 … #define MDIO_PHY_ID_PRTAD … #define MDIO_PHY_ID_DEVAD … #define MDIO_PHY_ID_C45_MASK … static inline __u16 mdio_phy_id_c45(int prtad, int devad) { … } /* UsxgmiiChannelInfo[15:0] for USXGMII in-band auto-negotiation.*/ #define MDIO_USXGMII_EEE_CLK_STP … #define MDIO_USXGMII_EEE … #define MDIO_USXGMII_SPD_MASK … #define MDIO_USXGMII_FULL_DUPLEX … #define MDIO_USXGMII_DPX_SPD_MASK … #define MDIO_USXGMII_10 … #define MDIO_USXGMII_10HALF … #define MDIO_USXGMII_10FULL … #define MDIO_USXGMII_100 … #define MDIO_USXGMII_100HALF … #define MDIO_USXGMII_100FULL … #define MDIO_USXGMII_1000 … #define MDIO_USXGMII_1000HALF … #define MDIO_USXGMII_1000FULL … #define MDIO_USXGMII_10G … #define MDIO_USXGMII_10GHALF … #define MDIO_USXGMII_10GFULL … #define MDIO_USXGMII_2500 … #define MDIO_USXGMII_2500HALF … #define MDIO_USXGMII_2500FULL … #define MDIO_USXGMII_5000 … #define MDIO_USXGMII_5000HALF … #define MDIO_USXGMII_5000FULL … #define MDIO_USXGMII_LINK … #endif /* _UAPI__LINUX_MDIO_H__ */
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