linux/drivers/phy/broadcom/phy-brcm-sata.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Broadcom SATA3 AHCI Controller PHY Driver
 *
 * Copyright (C) 2016 Broadcom
 */

#include <linux/delay.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>

#define SATA_PCB_BANK_OFFSET …
#define SATA_PCB_REG_OFFSET(ofs) …

#define MAX_PORTS …

/* Register offset between PHYs in PCB space */
#define SATA_PCB_REG_28NM_SPACE_SIZE …

/* The older SATA PHY registers duplicated per port registers within the map,
 * rather than having a separate map per port.
 */
#define SATA_PCB_REG_40NM_SPACE_SIZE …

/* Register offset between PHYs in PHY control space */
#define SATA_PHY_CTRL_REG_28NM_SPACE_SIZE …

enum brcm_sata_phy_version { … };

enum brcm_sata_phy_rxaeq_mode { … };

static enum brcm_sata_phy_rxaeq_mode rxaeq_to_val(const char *m)
{ … }

struct brcm_sata_port { … };

struct brcm_sata_phy { … };

enum sata_phy_regs { … };

enum sata_phy_ctrl_regs { … };

static inline void __iomem *brcm_sata_ctrl_base(struct brcm_sata_port *port)
{ … }

static void brcm_sata_phy_wr(struct brcm_sata_port *port, u32 bank,
			     u32 ofs, u32 msk, u32 value)
{ … }

static u32 brcm_sata_phy_rd(struct brcm_sata_port *port, u32 bank, u32 ofs)
{ … }

/* These defaults were characterized by H/W group */
#define STB_FMIN_VAL_DEFAULT …
#define STB_FMAX_VAL_DEFAULT …
#define STB_FMAX_VAL_SSC …

static void brcm_stb_sata_ssc_init(struct brcm_sata_port *port)
{ … }

#define AEQ_FRC_EQ_VAL_SHIFT …
#define AEQ_FRC_EQ_VAL_MASK …

static int brcm_stb_sata_rxaeq_init(struct brcm_sata_port *port)
{ … }

static int brcm_stb_sata_init(struct brcm_sata_port *port)
{ … }

static int brcm_stb_sata_16nm_ssc_init(struct brcm_sata_port *port)
{ … }

static int brcm_stb_sata_16nm_init(struct brcm_sata_port *port)
{ … }

/* NS2 SATA PLL1 defaults were characterized by H/W group */
#define NS2_PLL1_ACTRL2_MAGIC …
#define NS2_PLL1_ACTRL3_MAGIC …
#define NS2_PLL1_ACTRL4_MAGIC …

static int brcm_ns2_sata_init(struct brcm_sata_port *port)
{ … }

static int brcm_nsp_sata_init(struct brcm_sata_port *port)
{ … }

/* SR PHY PLL0 registers */
#define SR_PLL0_ACTRL6_MAGIC …

/* SR PHY PLL1 registers */
#define SR_PLL1_ACTRL2_MAGIC …
#define SR_PLL1_ACTRL3_MAGIC …
#define SR_PLL1_ACTRL4_MAGIC …

static int brcm_sr_sata_init(struct brcm_sata_port *port)
{ … }

static int brcm_dsl_sata_init(struct brcm_sata_port *port)
{ … }

static int brcm_sata_phy_init(struct phy *phy)
{ … }

static void brcm_stb_sata_calibrate(struct brcm_sata_port *port)
{ … }

static int brcm_sata_phy_calibrate(struct phy *phy)
{ … }

static const struct phy_ops phy_ops = …;

static const struct of_device_id brcm_sata_phy_of_match[] = …;
MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);

static int brcm_sata_phy_probe(struct platform_device *pdev)
{ … }

static struct platform_driver brcm_sata_phy_driver = …;
module_platform_driver(…) …;

MODULE_DESCRIPTION(…) …;
MODULE_LICENSE(…) …;
MODULE_AUTHOR(…) …;
MODULE_AUTHOR(…) …;
MODULE_ALIAS(…) …;