// SPDX-License-Identifier: GPL-2.0+ /* * Salvo PHY is a 28nm PHY, it is a legacy PHY, and only * for USB3 and USB2. * * Copyright (c) 2019-2020 NXP */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/io.h> #include <linux/module.h> #include <linux/phy/phy.h> #include <linux/platform_device.h> #include <linux/delay.h> #include <linux/of.h> #include <linux/of_platform.h> #define USB3_PHY_OFFSET … #define USB2_PHY_OFFSET … /* USB3 PHY register definition */ #define PHY_PMA_CMN_CTRL1 … #define TB_ADDR_CMN_DIAG_HSCLK_SEL … #define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR … #define TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR … #define TB_ADDR_CMN_PLL0_INTDIV … #define TB_ADDR_CMN_PLL0_FRACDIV … #define TB_ADDR_CMN_PLL0_HIGH_THR … #define TB_ADDR_CMN_PLL0_SS_CTRL1 … #define TB_ADDR_CMN_PLL0_SS_CTRL2 … #define TB_ADDR_CMN_PLL0_DSM_DIAG … #define TB_ADDR_CMN_DIAG_PLL0_OVRD … #define TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD … #define TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD … #define TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE … #define TB_ADDR_CMN_DIAG_PLL0_CP_TUNE … #define TB_ADDR_CMN_DIAG_PLL0_LF_PROG … #define TB_ADDR_CMN_DIAG_PLL0_TEST_MODE … #define TB_ADDR_CMN_PSM_CLK_CTRL … #define TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR … #define TB_ADDR_XCVR_PSM_RCTRL … #define TB_ADDR_TX_PSC_A0 … #define TB_ADDR_TX_PSC_A1 … #define TB_ADDR_TX_PSC_A2 … #define TB_ADDR_TX_PSC_A3 … #define TB_ADDR_TX_DIAG_ECTRL_OVRD … #define TB_ADDR_TX_PSC_CAL … #define TB_ADDR_TX_PSC_RDY … #define TB_ADDR_RX_PSC_A0 … #define TB_ADDR_RX_PSC_A1 … #define TB_ADDR_RX_PSC_A2 … #define TB_ADDR_RX_PSC_A3 … #define TB_ADDR_RX_PSC_CAL … #define TB_ADDR_RX_PSC_RDY … #define TB_ADDR_TX_TXCC_MGNLS_MULT_000 … #define TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY … #define TB_ADDR_RX_SLC_CU_ITER_TMR … #define TB_ADDR_RX_SIGDET_HL_FILT_TMR … #define TB_ADDR_RX_SAMP_DAC_CTRL … #define TB_ADDR_RX_DIAG_SIGDET_TUNE … #define TB_ADDR_RX_DIAG_LFPSDET_TUNE2 … #define TB_ADDR_RX_DIAG_BS_TM … #define TB_ADDR_RX_DIAG_DFE_CTRL1 … #define TB_ADDR_RX_DIAG_ILL_IQE_TRIM4 … #define TB_ADDR_RX_DIAG_ILL_E_TRIM0 … #define TB_ADDR_RX_DIAG_ILL_IQ_TRIM0 … #define TB_ADDR_RX_DIAG_ILL_IQE_TRIM6 … #define TB_ADDR_RX_DIAG_RXFE_TM3 … #define TB_ADDR_RX_DIAG_RXFE_TM4 … #define TB_ADDR_RX_DIAG_LFPSDET_TUNE … #define TB_ADDR_RX_DIAG_DFE_CTRL3 … #define TB_ADDR_RX_DIAG_SC2C_DELAY … #define TB_ADDR_RX_REE_VGA_GAIN_NODFE … #define TB_ADDR_XCVR_PSM_CAL_TMR … #define TB_ADDR_XCVR_PSM_A0BYP_TMR … #define TB_ADDR_XCVR_PSM_A0IN_TMR … #define TB_ADDR_XCVR_PSM_A1IN_TMR … #define TB_ADDR_XCVR_PSM_A2IN_TMR … #define TB_ADDR_XCVR_PSM_A3IN_TMR … #define TB_ADDR_XCVR_PSM_A4IN_TMR … #define TB_ADDR_XCVR_PSM_A5IN_TMR … #define TB_ADDR_XCVR_PSM_A0OUT_TMR … #define TB_ADDR_XCVR_PSM_A1OUT_TMR … #define TB_ADDR_XCVR_PSM_A2OUT_TMR … #define TB_ADDR_XCVR_PSM_A3OUT_TMR … #define TB_ADDR_XCVR_PSM_A4OUT_TMR … #define TB_ADDR_XCVR_PSM_A5OUT_TMR … #define TB_ADDR_TX_RCVDET_EN_TMR … #define TB_ADDR_TX_RCVDET_ST_TMR … #define TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR … #define TB_ADDR_TX_RCVDETSC_CTRL … /* USB2 PHY register definition */ #define UTMI_REG15 … #define UTMI_AFE_RX_REG0 … #define UTMI_AFE_RX_REG5 … #define UTMI_AFE_BC_REG4 … /* Align UTMI_AFE_RX_REG0 bit[7:6] define */ enum usb2_disconn_threshold { … }; #define RX_USB2_DISCONN_MASK … /* TB_ADDR_TX_RCVDETSC_CTRL */ #define RXDET_IN_P3_32KHZ … /* * UTMI_REG15 * * Gate how many us for the txvalid signal until analog * HS/FS transmitters have powered up */ #define TXVALID_GATE_THRESHOLD_HS_MASK … /* 0us, txvalid is ready just after HS/FS transmitters have powered up */ #define TXVALID_GATE_THRESHOLD_HS_0US … #define SET_B_SESSION_VALID … #define CLR_B_SESSION_VALID … struct cdns_reg_pairs { … }; struct cdns_salvo_data { … }; struct cdns_salvo_phy { … }; static const struct of_device_id cdns_salvo_phy_of_match[]; static const struct cdns_salvo_data cdns_nxp_salvo_data; static bool cdns_is_nxp_phy(struct cdns_salvo_phy *salvo_phy) { … } static u16 cdns_salvo_read(struct cdns_salvo_phy *salvo_phy, u32 offset, u32 reg) { … } static void cdns_salvo_write(struct cdns_salvo_phy *salvo_phy, u32 offset, u32 reg, u16 val) { … } /* * Below bringup sequence pair are from Cadence PHY's User Guide * and NXP platform tuning results. */ static const struct cdns_reg_pairs cdns_nxp_sequence_pair[] = …; static int cdns_salvo_phy_init(struct phy *phy) { … } static int cdns_salvo_phy_power_on(struct phy *phy) { … } static int cdns_salvo_phy_power_off(struct phy *phy) { … } static int cdns_salvo_set_mode(struct phy *phy, enum phy_mode mode, int submode) { … } static const struct phy_ops cdns_salvo_phy_ops = …; static int cdns_salvo_phy_probe(struct platform_device *pdev) { … } static const struct cdns_salvo_data cdns_nxp_salvo_data = …; static const struct of_device_id cdns_salvo_phy_of_match[] = …; MODULE_DEVICE_TABLE(of, cdns_salvo_phy_of_match); static struct platform_driver cdns_salvo_phy_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …; MODULE_DESCRIPTION(…) …;
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