// SPDX-License-Identifier: GPL-2.0-only /* * Cadence Torrent SD0801 PHY driver. * * Copyright 2018 Cadence Design Systems, Inc. * */ #include <dt-bindings/phy/phy.h> #include <dt-bindings/phy/phy-cadence.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> #include <linux/phy/phy.h> #include <linux/platform_device.h> #include <linux/reset.h> #include <linux/regmap.h> #define REF_CLK_19_2MHZ … #define REF_CLK_25MHZ … #define REF_CLK_100MHZ … #define REF_CLK_156_25MHZ … #define MAX_NUM_LANES … #define DEFAULT_MAX_BIT_RATE … #define POLL_TIMEOUT_US … #define PLL_LOCK_TIMEOUT … #define DP_PLL0 … #define DP_PLL1 … #define TORRENT_COMMON_CDB_OFFSET … #define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) … #define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) … #define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset) … #define TORRENT_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) … #define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset) … #define TORRENT_DPTX_PHY_OFFSET … /* * register offsets from DPTX PHY register block base (i.e MHDP * register base + 0x30a00) */ #define PHY_AUX_CTRL … #define PHY_RESET … #define PMA_TX_ELEC_IDLE_SHIFT … #define PHY_PMA_XCVR_PLLCLK_EN … #define PHY_PMA_XCVR_PLLCLK_EN_ACK … #define PHY_PMA_XCVR_POWER_STATE_REQ … #define PHY_POWER_STATE_LN(ln) … #define PMA_XCVR_POWER_STATE_REQ_LN_MASK … #define PHY_PMA_XCVR_POWER_STATE_ACK … #define PHY_PMA_CMN_READY … /* * register offsets from SD0801 PHY register block base (i.e MHDP * register base + 0x500000) */ #define CMN_SSM_BANDGAP_TMR … #define CMN_SSM_BIAS_TMR … #define CMN_PLLSM0_PLLPRE_TMR … #define CMN_PLLSM0_PLLLOCK_TMR … #define CMN_PLLSM1_PLLPRE_TMR … #define CMN_PLLSM1_PLLLOCK_TMR … #define CMN_CDIAG_CDB_PWRI_OVRD … #define CMN_CDIAG_XCVRC_PWRI_OVRD … #define CMN_CDIAG_REFCLK_OVRD … #define CMN_CDIAG_REFCLK_DRV0_CTRL … #define CMN_BGCAL_INIT_TMR … #define CMN_BGCAL_ITER_TMR … #define CMN_IBCAL_INIT_TMR … #define CMN_PLL0_VCOCAL_TCTRL … #define CMN_PLL0_VCOCAL_INIT_TMR … #define CMN_PLL0_VCOCAL_ITER_TMR … #define CMN_PLL0_VCOCAL_REFTIM_START … #define CMN_PLL0_VCOCAL_PLLCNT_START … #define CMN_PLL0_INTDIV_M0 … #define CMN_PLL0_FRACDIVL_M0 … #define CMN_PLL0_FRACDIVH_M0 … #define CMN_PLL0_HIGH_THR_M0 … #define CMN_PLL0_DSM_DIAG_M0 … #define CMN_PLL0_DSM_FBH_OVRD_M0 … #define CMN_PLL0_DSM_FBL_OVRD_M0 … #define CMN_PLL0_SS_CTRL1_M0 … #define CMN_PLL0_SS_CTRL2_M0 … #define CMN_PLL0_SS_CTRL3_M0 … #define CMN_PLL0_SS_CTRL4_M0 … #define CMN_PLL0_LOCK_REFCNT_START … #define CMN_PLL0_LOCK_PLLCNT_START … #define CMN_PLL0_LOCK_PLLCNT_THR … #define CMN_PLL0_INTDIV_M1 … #define CMN_PLL0_FRACDIVH_M1 … #define CMN_PLL0_HIGH_THR_M1 … #define CMN_PLL0_DSM_DIAG_M1 … #define CMN_PLL0_SS_CTRL1_M1 … #define CMN_PLL0_SS_CTRL2_M1 … #define CMN_PLL0_SS_CTRL3_M1 … #define CMN_PLL0_SS_CTRL4_M1 … #define CMN_PLL1_VCOCAL_TCTRL … #define CMN_PLL1_VCOCAL_INIT_TMR … #define CMN_PLL1_VCOCAL_ITER_TMR … #define CMN_PLL1_VCOCAL_REFTIM_START … #define CMN_PLL1_VCOCAL_PLLCNT_START … #define CMN_PLL1_INTDIV_M0 … #define CMN_PLL1_FRACDIVL_M0 … #define CMN_PLL1_FRACDIVH_M0 … #define CMN_PLL1_HIGH_THR_M0 … #define CMN_PLL1_DSM_DIAG_M0 … #define CMN_PLL1_DSM_FBH_OVRD_M0 … #define CMN_PLL1_DSM_FBL_OVRD_M0 … #define CMN_PLL1_SS_CTRL1_M0 … #define CMN_PLL1_SS_CTRL2_M0 … #define CMN_PLL1_SS_CTRL3_M0 … #define CMN_PLL1_SS_CTRL4_M0 … #define CMN_PLL1_LOCK_REFCNT_START … #define CMN_PLL1_LOCK_PLLCNT_START … #define CMN_PLL1_LOCK_PLLCNT_THR … #define CMN_TXPUCAL_TUNE … #define CMN_TXPUCAL_INIT_TMR … #define CMN_TXPUCAL_ITER_TMR … #define CMN_TXPDCAL_TUNE … #define CMN_TXPDCAL_INIT_TMR … #define CMN_TXPDCAL_ITER_TMR … #define CMN_RXCAL_INIT_TMR … #define CMN_RXCAL_ITER_TMR … #define CMN_SD_CAL_INIT_TMR … #define CMN_SD_CAL_ITER_TMR … #define CMN_SD_CAL_REFTIM_START … #define CMN_SD_CAL_PLLCNT_START … #define CMN_PDIAG_PLL0_CTRL_M0 … #define CMN_PDIAG_PLL0_CLK_SEL_M0 … #define CMN_PDIAG_PLL0_CP_PADJ_M0 … #define CMN_PDIAG_PLL0_CP_IADJ_M0 … #define CMN_PDIAG_PLL0_FILT_PADJ_M0 … #define CMN_PDIAG_PLL0_CTRL_M1 … #define CMN_PDIAG_PLL0_CLK_SEL_M1 … #define CMN_PDIAG_PLL0_CP_PADJ_M1 … #define CMN_PDIAG_PLL0_CP_IADJ_M1 … #define CMN_PDIAG_PLL0_FILT_PADJ_M1 … #define CMN_PDIAG_PLL1_CTRL_M0 … #define CMN_PDIAG_PLL1_CLK_SEL_M0 … #define CMN_PDIAG_PLL1_CP_PADJ_M0 … #define CMN_PDIAG_PLL1_CP_IADJ_M0 … #define CMN_PDIAG_PLL1_FILT_PADJ_M0 … #define CMN_DIAG_BIAS_OVRD1 … /* PMA TX Lane registers */ #define TX_TXCC_CTRL … #define TX_TXCC_CPOST_MULT_00 … #define TX_TXCC_CPOST_MULT_01 … #define TX_TXCC_MGNFS_MULT_000 … #define TX_TXCC_MGNFS_MULT_100 … #define DRV_DIAG_TX_DRV … #define XCVR_DIAG_PLLDRC_CTRL … #define XCVR_DIAG_HSCLK_SEL … #define XCVR_DIAG_HSCLK_DIV … #define XCVR_DIAG_RXCLK_CTRL … #define XCVR_DIAG_BIDI_CTRL … #define XCVR_DIAG_PSC_OVRD … #define TX_PSC_A0 … #define TX_PSC_A1 … #define TX_PSC_A2 … #define TX_PSC_A3 … #define TX_RCVDET_ST_TMR … #define TX_DIAG_ACYA … #define TX_DIAG_ACYA_HBDC_MASK … /* PMA RX Lane registers */ #define RX_PSC_A0 … #define RX_PSC_A1 … #define RX_PSC_A2 … #define RX_PSC_A3 … #define RX_PSC_CAL … #define RX_SDCAL0_INIT_TMR … #define RX_SDCAL0_ITER_TMR … #define RX_SDCAL1_INIT_TMR … #define RX_SDCAL1_ITER_TMR … #define RX_CDRLF_CNFG … #define RX_CDRLF_CNFG3 … #define RX_SIGDET_HL_FILT_TMR … #define RX_REE_GCSM1_CTRL … #define RX_REE_GCSM1_EQENM_PH1 … #define RX_REE_GCSM1_EQENM_PH2 … #define RX_REE_GCSM2_CTRL … #define RX_REE_PERGCSM_CTRL … #define RX_REE_ATTEN_THR … #define RX_REE_TAP1_CLIP … #define RX_REE_TAP2TON_CLIP … #define RX_REE_SMGM_CTRL1 … #define RX_REE_SMGM_CTRL2 … #define RX_DIAG_DFE_CTRL … #define RX_DIAG_DFE_AMP_TUNE_2 … #define RX_DIAG_DFE_AMP_TUNE_3 … #define RX_DIAG_NQST_CTRL … #define RX_DIAG_SIGDET_TUNE … #define RX_DIAG_PI_RATE … #define RX_DIAG_PI_CAP … #define RX_DIAG_ACYA … /* PHY PCS common registers */ #define PHY_PIPE_CMN_CTRL1 … #define PHY_PLL_CFG … #define PHY_PIPE_USB3_GEN2_PRE_CFG0 … #define PHY_PIPE_USB3_GEN2_POST_CFG0 … #define PHY_PIPE_USB3_GEN2_POST_CFG1 … /* PHY PCS lane registers */ #define PHY_PCS_ISO_LINK_CTRL … /* PHY PMA common registers */ #define PHY_PMA_CMN_CTRL1 … #define PHY_PMA_CMN_CTRL2 … #define PHY_PMA_PLL_RAW_CTRL … #define CDNS_TORRENT_OUTPUT_CLOCKS … static const char * const clk_names[] = …; static const struct reg_field phy_pll_cfg = …; static const struct reg_field phy_pma_cmn_ctrl_1 = …; static const struct reg_field phy_pma_cmn_ctrl_2 = …; static const struct reg_field phy_pma_pll_raw_ctrl = …; static const struct reg_field phy_reset_ctrl = …; static const struct reg_field phy_pcs_iso_link_ctrl_1 = …; static const struct reg_field phy_pipe_cmn_ctrl1_0 = …; static const struct reg_field cmn_cdiag_refclk_ovrd_4 = …; #define REFCLK_OUT_NUM_CMN_CONFIG … enum cdns_torrent_refclk_out_cmn { … }; static const struct reg_field refclk_out_cmn_cfg[] = …; static const int refclk_driver_parent_index[] = …; static u32 cdns_torrent_refclk_driver_mux_table[] = …; enum cdns_torrent_phy_type { … }; enum cdns_torrent_ref_clk { … }; enum cdns_torrent_ssc_mode { … }; /* Unique key id for vals table entry * REFCLK0_RATE | REFCLK1_RATE | LINK0_TYPE | LINK1_TYPE | SSC_TYPE */ #define REFCLK0_SHIFT … #define REFCLK0_MASK … #define REFCLK1_SHIFT … #define REFCLK1_MASK … #define LINK0_SHIFT … #define LINK0_MASK … #define LINK1_SHIFT … #define LINK1_MASK … #define SSC_SHIFT … #define SSC_MASK … #define CDNS_TORRENT_KEY(refclk0, refclk1, link0, link1, ssc) … #define CDNS_TORRENT_KEY_ANYCLK(link0, link1) … struct cdns_torrent_inst { … }; struct cdns_torrent_phy { … }; enum phy_powerstate { … }; struct cdns_torrent_refclk_driver { … }; #define to_cdns_torrent_refclk_driver(_hw) … struct cdns_torrent_derived_refclk { … }; #define to_cdns_torrent_derived_refclk(_hw) … struct cdns_torrent_received_refclk { … }; #define to_cdns_torrent_received_refclk(_hw) … struct cdns_reg_pairs { … }; struct cdns_torrent_vals { … }; struct cdns_torrent_vals_entry { … }; struct cdns_torrent_vals_table { … }; struct cdns_torrent_data { … }; struct cdns_regmap_cdb_context { … }; static struct cdns_torrent_vals *cdns_torrent_get_tbl_vals(const struct cdns_torrent_vals_table *tbl, enum cdns_torrent_ref_clk refclk0, enum cdns_torrent_ref_clk refclk1, enum cdns_torrent_phy_type link0, enum cdns_torrent_phy_type link1, enum cdns_torrent_ssc_mode ssc) { … } static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val) { … } static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val) { … } static int cdns_regmap_dptx_write(void *context, unsigned int reg, unsigned int val) { … } static int cdns_regmap_dptx_read(void *context, unsigned int reg, unsigned int *val) { … } #define TORRENT_TX_LANE_CDB_REGMAP_CONF(n) … #define TORRENT_RX_LANE_CDB_REGMAP_CONF(n) … static const struct regmap_config cdns_torrent_tx_lane_cdb_config[] = …; static const struct regmap_config cdns_torrent_rx_lane_cdb_config[] = …; static const struct regmap_config cdns_torrent_common_cdb_config = …; #define TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF(n) … static const struct regmap_config cdns_torrent_phy_pcs_lane_cdb_config[] = …; static const struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = …; static const struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = …; static const struct regmap_config cdns_torrent_dptx_phy_config = …; /* PHY mmr access functions */ static void cdns_torrent_phy_write(struct regmap *regmap, u32 offset, u32 val) { … } static u32 cdns_torrent_phy_read(struct regmap *regmap, u32 offset) { … } /* DPTX mmr access functions */ static void cdns_torrent_dp_write(struct regmap *regmap, u32 offset, u32 val) { … } static u32 cdns_torrent_dp_read(struct regmap *regmap, u32 offset) { … } /* * Structure used to store values of PHY registers for voltage-related * coefficients, for particular voltage swing and pre-emphasis level. Values * are shared across all physical lanes. */ struct coefficients { … }; /* * Array consists of values of voltage-related registers for sd0801 PHY. A value * of 0xFFFF is a placeholder for invalid combination, and will never be used. */ static const struct coefficients vltg_coeff[4][4] = …; static const char *cdns_torrent_get_phy_type(enum cdns_torrent_phy_type phy_type) { … } /* * Set registers responsible for enabling and configuring SSC, with second and * third register values provided by parameters. */ static void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy, u32 ctrl2_val, u32 ctrl3_val) { … } static void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy, u32 rate, bool ssc) { … } /* * Set registers responsible for enabling and configuring SSC, with second * register value provided by a parameter. */ static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy, u32 ctrl2_val) { … } static void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy, u32 rate, bool ssc) { … } static void cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(struct cdns_torrent_phy *cdns_phy, u32 rate, bool ssc) { … } /* Set PLL used for DP configuration */ static int cdns_torrent_dp_get_pll(struct cdns_torrent_phy *cdns_phy, enum cdns_torrent_phy_type phy_t2) { … } /* * Enable or disable PLL for selected lanes. */ static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy, struct cdns_torrent_inst *inst, struct phy_configure_opts_dp *dp, bool enable) { … } static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy, struct cdns_torrent_inst *inst, u32 num_lanes, enum phy_powerstate powerstate) { … } static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, struct cdns_torrent_inst *inst, u32 num_lanes) { … } static int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy) { … } static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy, struct cdns_torrent_inst *inst, u32 rate, u32 num_lanes) { … } /* * Perform register operations related to setting link rate, once powerstate is * set and PLL disable request was processed. */ static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy, struct cdns_torrent_inst *inst, struct phy_configure_opts_dp *dp) { … } /* * Verify, that parameters to configure PHY with are correct. */ static int cdns_torrent_dp_verify_config(struct cdns_torrent_inst *inst, struct phy_configure_opts_dp *dp) { … } /* Set power state A0 and PLL clock enable to 0 on enabled lanes. */ static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy, struct cdns_torrent_inst *inst, u32 num_lanes) { … } /* Configure lane count as required. */ static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy, struct cdns_torrent_inst *inst, struct phy_configure_opts_dp *dp) { … } /* Configure link rate as required. */ static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy, struct cdns_torrent_inst *inst, struct phy_configure_opts_dp *dp) { … } /* Configure voltage swing and pre-emphasis for all enabled lanes. */ static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy, struct cdns_torrent_inst *inst, struct phy_configure_opts_dp *dp) { u8 lane; u16 val; for (lane = 0; lane < dp->lanes; lane++) { val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], TX_DIAG_ACYA); /* * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the * current state of the analog TX driver. */ val |= TX_DIAG_ACYA_HBDC_MASK; cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], TX_DIAG_ACYA, val); cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], TX_TXCC_CTRL, 0x08A4); val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv; cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], DRV_DIAG_TX_DRV, val); val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult; cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], TX_TXCC_MGNFS_MULT_000, val); val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult; cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], TX_TXCC_CPOST_MULT_00, val); val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], TX_DIAG_ACYA); /* * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of * analog TX driver to reflect the new programmed one. */ val &= ~TX_DIAG_ACYA_HBDC_MASK; cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], TX_DIAG_ACYA, val); } }; static int cdns_torrent_dp_configure(struct phy *phy, union phy_configure_opts *opts) { … } static int cdns_torrent_phy_on(struct phy *phy) { … } static int cdns_torrent_phy_off(struct phy *phy) { … } static void cdns_torrent_dp_common_init(struct cdns_torrent_phy *cdns_phy, struct cdns_torrent_inst *inst) { … } static int cdns_torrent_dp_start(struct cdns_torrent_phy *cdns_phy, struct cdns_torrent_inst *inst, struct phy *phy) { … } static int cdns_torrent_dp_init(struct phy *phy) { … } static int cdns_torrent_dp_multilink_init(struct cdns_torrent_phy *cdns_phy, struct cdns_torrent_inst *inst, struct phy *phy) { … } static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw) { … } static void cdns_torrent_derived_refclk_disable(struct clk_hw *hw) { … } static int cdns_torrent_derived_refclk_is_enabled(struct clk_hw *hw) { … } static const struct clk_ops cdns_torrent_derived_refclk_ops = …; static int cdns_torrent_derived_refclk_register(struct cdns_torrent_phy *cdns_phy) { … } static int cdns_torrent_received_refclk_enable(struct clk_hw *hw) { … } static void cdns_torrent_received_refclk_disable(struct clk_hw *hw) { … } static int cdns_torrent_received_refclk_is_enabled(struct clk_hw *hw) { … } static const struct clk_ops cdns_torrent_received_refclk_ops = …; static int cdns_torrent_received_refclk_register(struct cdns_torrent_phy *cdns_phy) { … } static int cdns_torrent_refclk_driver_enable(struct clk_hw *hw) { … } static void cdns_torrent_refclk_driver_disable(struct clk_hw *hw) { … } static int cdns_torrent_refclk_driver_is_enabled(struct clk_hw *hw) { … } static u8 cdns_torrent_refclk_driver_get_parent(struct clk_hw *hw) { … } static int cdns_torrent_refclk_driver_set_parent(struct clk_hw *hw, u8 index) { … } static const struct clk_ops cdns_torrent_refclk_driver_ops = …; static int cdns_torrent_refclk_driver_register(struct cdns_torrent_phy *cdns_phy) { … } static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base, u32 block_offset, u8 reg_offset_shift, const struct regmap_config *config) { … } static int cdns_torrent_dp_regfield_init(struct cdns_torrent_phy *cdns_phy) { … } static int cdns_torrent_regfield_init(struct cdns_torrent_phy *cdns_phy) { … } static int cdns_torrent_dp_regmap_init(struct cdns_torrent_phy *cdns_phy) { … } static int cdns_torrent_regmap_init(struct cdns_torrent_phy *cdns_phy) { … } static int cdns_torrent_phy_init(struct phy *phy) { … } static const struct phy_ops cdns_torrent_phy_ops = …; static int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy) { … } static void cdns_torrent_clk_cleanup(struct cdns_torrent_phy *cdns_phy) { … } static int cdns_torrent_clk_register(struct cdns_torrent_phy *cdns_phy) { … } static int cdns_torrent_of_get_reset(struct cdns_torrent_phy *cdns_phy) { … } static int cdns_torrent_of_get_clk(struct cdns_torrent_phy *cdns_phy) { … } static int cdns_torrent_clk(struct cdns_torrent_phy *cdns_phy) { … } static int cdns_torrent_phy_probe(struct platform_device *pdev) { … } static void cdns_torrent_phy_remove(struct platform_device *pdev) { … } /* SGMII and QSGMII link configuration */ static struct cdns_reg_pairs sgmii_qsgmii_link_cmn_regs[] = …; static struct cdns_reg_pairs sgmii_qsgmii_xcvr_diag_ln_regs[] = …; static struct cdns_torrent_vals sgmii_qsgmii_link_cmn_vals = …; static struct cdns_torrent_vals sgmii_qsgmii_xcvr_diag_ln_vals = …; static int cdns_torrent_phy_suspend_noirq(struct device *dev) { … } static int cdns_torrent_phy_resume_noirq(struct device *dev) { … } static DEFINE_NOIRQ_DEV_PM_OPS(cdns_torrent_phy_pm_ops, cdns_torrent_phy_suspend_noirq, cdns_torrent_phy_resume_noirq); /* USB and DP link configuration */ static struct cdns_reg_pairs usb_dp_link_cmn_regs[] = …; static struct cdns_reg_pairs usb_dp_xcvr_diag_ln_regs[] = …; static struct cdns_reg_pairs dp_usb_xcvr_diag_ln_regs[] = …; static struct cdns_torrent_vals usb_dp_link_cmn_vals = …; static struct cdns_torrent_vals usb_dp_xcvr_diag_ln_vals = …; static struct cdns_torrent_vals dp_usb_xcvr_diag_ln_vals = …; /* USXGMII and SGMII/QSGMII link configuration */ static struct cdns_reg_pairs usxgmii_sgmii_link_cmn_regs[] = …; static struct cdns_reg_pairs usxgmii_sgmii_xcvr_diag_ln_regs[] = …; static struct cdns_reg_pairs sgmii_usxgmii_xcvr_diag_ln_regs[] = …; static struct cdns_torrent_vals usxgmii_sgmii_link_cmn_vals = …; static struct cdns_torrent_vals usxgmii_sgmii_xcvr_diag_ln_vals = …; static struct cdns_torrent_vals sgmii_usxgmii_xcvr_diag_ln_vals = …; /* Multilink USXGMII, using PLL0, 156.25 MHz Ref clk, no SSC */ static struct cdns_reg_pairs ml_usxgmii_pll0_156_25_no_ssc_cmn_regs[] = …; static struct cdns_torrent_vals ml_usxgmii_pll0_156_25_no_ssc_cmn_vals = …; /* Multilink SGMII/QSGMII, using PLL1, 100 MHz Ref clk, no SSC */ static struct cdns_reg_pairs ml_sgmii_pll1_100_no_ssc_cmn_regs[] = …; static struct cdns_torrent_vals ml_sgmii_pll1_100_no_ssc_cmn_vals = …; /* TI J7200, Multilink USXGMII, using PLL0, 156.25 MHz Ref clk, no SSC */ static struct cdns_reg_pairs j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_regs[] = …; static struct cdns_torrent_vals j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_vals = …; /* TI J7200, Multilink SGMII/QSGMII, using PLL1, 100 MHz Ref clk, no SSC */ static struct cdns_reg_pairs j7200_ml_sgmii_pll1_100_no_ssc_cmn_regs[] = …; static struct cdns_torrent_vals j7200_ml_sgmii_pll1_100_no_ssc_cmn_vals = …; /* PCIe and USXGMII link configuration */ static struct cdns_reg_pairs pcie_usxgmii_link_cmn_regs[] = …; static struct cdns_reg_pairs pcie_usxgmii_xcvr_diag_ln_regs[] = …; static struct cdns_reg_pairs usxgmii_pcie_xcvr_diag_ln_regs[] = …; static struct cdns_torrent_vals pcie_usxgmii_link_cmn_vals = …; static struct cdns_torrent_vals pcie_usxgmii_xcvr_diag_ln_vals = …; static struct cdns_torrent_vals usxgmii_pcie_xcvr_diag_ln_vals = …; /* * Multilink USXGMII, using PLL1, 156.25 MHz Ref clk, no SSC */ static struct cdns_reg_pairs ml_usxgmii_pll1_156_25_no_ssc_cmn_regs[] = …; static struct cdns_reg_pairs ml_usxgmii_156_25_no_ssc_tx_ln_regs[] = …; static struct cdns_reg_pairs ml_usxgmii_156_25_no_ssc_rx_ln_regs[] = …; static struct cdns_torrent_vals ml_usxgmii_pll1_156_25_no_ssc_cmn_vals = …; static struct cdns_torrent_vals ml_usxgmii_156_25_no_ssc_tx_ln_vals = …; static struct cdns_torrent_vals ml_usxgmii_156_25_no_ssc_rx_ln_vals = …; /* TI USXGMII configuration: Enable cmn_refclk_rcv_out_en */ static struct cdns_reg_pairs ti_usxgmii_phy_pma_cmn_regs[] = …; static struct cdns_torrent_vals ti_usxgmii_phy_pma_cmn_vals = …; /* Single USXGMII link configuration */ static struct cdns_reg_pairs sl_usxgmii_link_cmn_regs[] = …; static struct cdns_reg_pairs sl_usxgmii_xcvr_diag_ln_regs[] = …; static struct cdns_torrent_vals sl_usxgmii_link_cmn_vals = …; static struct cdns_torrent_vals sl_usxgmii_xcvr_diag_ln_vals = …; /* Single link USXGMII, 156.25 MHz Ref clk, no SSC */ static struct cdns_reg_pairs sl_usxgmii_156_25_no_ssc_cmn_regs[] = …; static struct cdns_reg_pairs usxgmii_156_25_no_ssc_tx_ln_regs[] = …; static struct cdns_reg_pairs usxgmii_156_25_no_ssc_rx_ln_regs[] = …; static struct cdns_torrent_vals sl_usxgmii_156_25_no_ssc_cmn_vals = …; static struct cdns_torrent_vals usxgmii_156_25_no_ssc_tx_ln_vals = …; static struct cdns_torrent_vals usxgmii_156_25_no_ssc_rx_ln_vals = …; /* PCIe and DP link configuration */ static struct cdns_reg_pairs pcie_dp_link_cmn_regs[] = …; static struct cdns_reg_pairs pcie_dp_xcvr_diag_ln_regs[] = …; static struct cdns_reg_pairs dp_pcie_xcvr_diag_ln_regs[] = …; static struct cdns_torrent_vals pcie_dp_link_cmn_vals = …; static struct cdns_torrent_vals pcie_dp_xcvr_diag_ln_vals = …; static struct cdns_torrent_vals dp_pcie_xcvr_diag_ln_vals = …; /* DP Multilink, 100 MHz Ref clk, no SSC */ static struct cdns_reg_pairs dp_100_no_ssc_cmn_regs[] = …; static struct cdns_reg_pairs dp_100_no_ssc_tx_ln_regs[] = …; static struct cdns_reg_pairs dp_100_no_ssc_rx_ln_regs[] = …; static struct cdns_torrent_vals dp_100_no_ssc_cmn_vals = …; static struct cdns_torrent_vals dp_100_no_ssc_tx_ln_vals = …; static struct cdns_torrent_vals dp_100_no_ssc_rx_ln_vals = …; /* Single DisplayPort(DP) link configuration */ static struct cdns_reg_pairs sl_dp_link_cmn_regs[] = …; static struct cdns_reg_pairs sl_dp_xcvr_diag_ln_regs[] = …; static struct cdns_torrent_vals sl_dp_link_cmn_vals = …; static struct cdns_torrent_vals sl_dp_xcvr_diag_ln_vals = …; /* Single DP, 19.2 MHz Ref clk, no SSC */ static struct cdns_reg_pairs sl_dp_19_2_no_ssc_cmn_regs[] = …; static struct cdns_reg_pairs sl_dp_19_2_no_ssc_tx_ln_regs[] = …; static struct cdns_reg_pairs sl_dp_19_2_no_ssc_rx_ln_regs[] = …; static struct cdns_torrent_vals sl_dp_19_2_no_ssc_cmn_vals = …; static struct cdns_torrent_vals sl_dp_19_2_no_ssc_tx_ln_vals = …; static struct cdns_torrent_vals sl_dp_19_2_no_ssc_rx_ln_vals = …; /* Single DP, 25 MHz Ref clk, no SSC */ static struct cdns_reg_pairs sl_dp_25_no_ssc_cmn_regs[] = …; static struct cdns_reg_pairs sl_dp_25_no_ssc_tx_ln_regs[] = …; static struct cdns_reg_pairs sl_dp_25_no_ssc_rx_ln_regs[] = …; static struct cdns_torrent_vals sl_dp_25_no_ssc_cmn_vals = …; static struct cdns_torrent_vals sl_dp_25_no_ssc_tx_ln_vals = …; static struct cdns_torrent_vals sl_dp_25_no_ssc_rx_ln_vals = …; /* Single DP, 100 MHz Ref clk, no SSC */ static struct cdns_reg_pairs sl_dp_100_no_ssc_cmn_regs[] = …; static struct cdns_reg_pairs sl_dp_100_no_ssc_tx_ln_regs[] = …; static struct cdns_reg_pairs sl_dp_100_no_ssc_rx_ln_regs[] = …; static struct cdns_torrent_vals sl_dp_100_no_ssc_cmn_vals = …; static struct cdns_torrent_vals sl_dp_100_no_ssc_tx_ln_vals = …; static struct cdns_torrent_vals sl_dp_100_no_ssc_rx_ln_vals = …; /* USB and SGMII/QSGMII link configuration */ static struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = …; static struct cdns_reg_pairs usb_sgmii_xcvr_diag_ln_regs[] = …; static struct cdns_reg_pairs sgmii_usb_xcvr_diag_ln_regs[] = …; static struct cdns_torrent_vals usb_sgmii_link_cmn_vals = …; static struct cdns_torrent_vals usb_sgmii_xcvr_diag_ln_vals = …; static struct cdns_torrent_vals sgmii_usb_xcvr_diag_ln_vals = …; /* PCIe and USB Unique SSC link configuration */ static struct cdns_reg_pairs pcie_usb_link_cmn_regs[] = …; static struct cdns_reg_pairs pcie_usb_xcvr_diag_ln_regs[] = …; static struct cdns_reg_pairs usb_pcie_xcvr_diag_ln_regs[] = …; static struct cdns_torrent_vals pcie_usb_link_cmn_vals = …; static struct cdns_torrent_vals pcie_usb_xcvr_diag_ln_vals = …; static struct cdns_torrent_vals usb_pcie_xcvr_diag_ln_vals = …; /* USB 100 MHz Ref clk, internal SSC */ static struct cdns_reg_pairs usb_100_int_ssc_cmn_regs[] = …; static struct cdns_torrent_vals usb_100_int_ssc_cmn_vals = …; /* Single USB link configuration */ static struct cdns_reg_pairs sl_usb_link_cmn_regs[] = …; static struct cdns_reg_pairs sl_usb_xcvr_diag_ln_regs[] = …; static struct cdns_torrent_vals sl_usb_link_cmn_vals = …; static struct cdns_torrent_vals sl_usb_xcvr_diag_ln_vals = …; /* USB PHY PCS common configuration */ static struct cdns_reg_pairs usb_phy_pcs_cmn_regs[] = …; static struct cdns_torrent_vals usb_phy_pcs_cmn_vals = …; /* USB 100 MHz Ref clk, no SSC */ static struct cdns_reg_pairs sl_usb_100_no_ssc_cmn_regs[] = …; static struct cdns_torrent_vals sl_usb_100_no_ssc_cmn_vals = …; static struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = …; static struct cdns_reg_pairs usb_100_no_ssc_tx_ln_regs[] = …; static struct cdns_reg_pairs usb_100_no_ssc_rx_ln_regs[] = …; static struct cdns_torrent_vals usb_100_no_ssc_cmn_vals = …; static struct cdns_torrent_vals usb_100_no_ssc_tx_ln_vals = …; static struct cdns_torrent_vals usb_100_no_ssc_rx_ln_vals = …; /* Single link USB, 100 MHz Ref clk, internal SSC */ static struct cdns_reg_pairs sl_usb_100_int_ssc_cmn_regs[] = …; static struct cdns_torrent_vals sl_usb_100_int_ssc_cmn_vals = …; /* PCIe and SGMII/QSGMII Unique SSC link configuration */ static struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = …; static struct cdns_reg_pairs pcie_sgmii_xcvr_diag_ln_regs[] = …; static struct cdns_reg_pairs sgmii_pcie_xcvr_diag_ln_regs[] = …; static struct cdns_torrent_vals pcie_sgmii_link_cmn_vals = …; static struct cdns_torrent_vals pcie_sgmii_xcvr_diag_ln_vals = …; static struct cdns_torrent_vals sgmii_pcie_xcvr_diag_ln_vals = …; /* SGMII 100 MHz Ref clk, no SSC */ static struct cdns_reg_pairs sl_sgmii_100_no_ssc_cmn_regs[] = …; static struct cdns_torrent_vals sl_sgmii_100_no_ssc_cmn_vals = …; static struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = …; static struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = …; static struct cdns_reg_pairs ti_sgmii_100_no_ssc_tx_ln_regs[] = …; static struct cdns_reg_pairs sgmii_100_no_ssc_rx_ln_regs[] = …; static struct cdns_torrent_vals sgmii_100_no_ssc_cmn_vals = …; static struct cdns_torrent_vals sgmii_100_no_ssc_tx_ln_vals = …; static struct cdns_torrent_vals ti_sgmii_100_no_ssc_tx_ln_vals = …; static struct cdns_torrent_vals sgmii_100_no_ssc_rx_ln_vals = …; /* TI J7200, multilink SGMII */ static struct cdns_reg_pairs j7200_sgmii_100_no_ssc_tx_ln_regs[] = …; static struct cdns_torrent_vals j7200_sgmii_100_no_ssc_tx_ln_vals = …; static struct cdns_reg_pairs j7200_sgmii_100_no_ssc_rx_ln_regs[] = …; static struct cdns_torrent_vals j7200_sgmii_100_no_ssc_rx_ln_vals = …; /* SGMII 100 MHz Ref clk, internal SSC */ static struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = …; static struct cdns_torrent_vals sgmii_100_int_ssc_cmn_vals = …; /* QSGMII 100 MHz Ref clk, no SSC */ static struct cdns_reg_pairs sl_qsgmii_100_no_ssc_cmn_regs[] = …; static struct cdns_torrent_vals sl_qsgmii_100_no_ssc_cmn_vals = …; static struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = …; static struct cdns_reg_pairs qsgmii_100_no_ssc_tx_ln_regs[] = …; static struct cdns_reg_pairs ti_qsgmii_100_no_ssc_tx_ln_regs[] = …; static struct cdns_reg_pairs qsgmii_100_no_ssc_rx_ln_regs[] = …; static struct cdns_torrent_vals qsgmii_100_no_ssc_cmn_vals = …; static struct cdns_torrent_vals qsgmii_100_no_ssc_tx_ln_vals = …; static struct cdns_torrent_vals ti_qsgmii_100_no_ssc_tx_ln_vals = …; static struct cdns_torrent_vals qsgmii_100_no_ssc_rx_ln_vals = …; /* TI J7200, multilink QSGMII */ static struct cdns_reg_pairs j7200_qsgmii_100_no_ssc_tx_ln_regs[] = …; static struct cdns_torrent_vals j7200_qsgmii_100_no_ssc_tx_ln_vals = …; static struct cdns_reg_pairs j7200_qsgmii_100_no_ssc_rx_ln_regs[] = …; static struct cdns_torrent_vals j7200_qsgmii_100_no_ssc_rx_ln_vals = …; /* QSGMII 100 MHz Ref clk, internal SSC */ static struct cdns_reg_pairs qsgmii_100_int_ssc_cmn_regs[] = …; static struct cdns_torrent_vals qsgmii_100_int_ssc_cmn_vals = …; /* Single SGMII/QSGMII link configuration */ static struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = …; static struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = …; static struct cdns_torrent_vals sl_sgmii_link_cmn_vals = …; static struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = …; /* Multi link PCIe, 100 MHz Ref clk, internal SSC */ static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = …; static struct cdns_torrent_vals pcie_100_int_ssc_cmn_vals = …; /* Single link PCIe, 100 MHz Ref clk, internal SSC */ static struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = …; static struct cdns_torrent_vals sl_pcie_100_int_ssc_cmn_vals = …; /* PCIe, 100 MHz Ref clk, no SSC & external SSC */ static struct cdns_reg_pairs pcie_100_ext_no_ssc_cmn_regs[] = …; static struct cdns_reg_pairs pcie_100_ext_no_ssc_rx_ln_regs[] = …; static struct cdns_torrent_vals pcie_100_no_ssc_cmn_vals = …; static struct cdns_torrent_vals pcie_100_no_ssc_rx_ln_vals = …; static struct cdns_torrent_vals_entry link_cmn_vals_entries[] = …; static struct cdns_torrent_vals_entry xcvr_diag_vals_entries[] = …; static struct cdns_torrent_vals_entry pcs_cmn_vals_entries[] = …; static struct cdns_torrent_vals_entry cmn_vals_entries[] = …; static struct cdns_torrent_vals_entry cdns_tx_ln_vals_entries[] = …; static struct cdns_torrent_vals_entry cdns_rx_ln_vals_entries[] = …; static const struct cdns_torrent_data cdns_map_torrent = …; static struct cdns_torrent_vals_entry j721e_phy_pma_cmn_vals_entries[] = …; static struct cdns_torrent_vals_entry ti_tx_ln_vals_entries[] = …; static const struct cdns_torrent_data ti_j721e_map_torrent = …; /* TI J7200 (Torrent SD0805) */ static struct cdns_torrent_vals_entry ti_j7200_cmn_vals_entries[] = …; static struct cdns_torrent_vals_entry ti_j7200_tx_ln_vals_entries[] = …; static struct cdns_torrent_vals_entry ti_j7200_rx_ln_vals_entries[] = …; static const struct cdns_torrent_data ti_j7200_map_torrent = …; static const struct of_device_id cdns_torrent_phy_of_match[] = …; MODULE_DEVICE_TABLE(of, cdns_torrent_phy_of_match); static struct platform_driver cdns_torrent_phy_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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