// SPDX-License-Identifier: GPL-2.0 /* * Cadence Sierra PHY Driver * * Copyright (c) 2018 Cadence Design Systems * Author: Alan Douglas <[email protected]> * */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/io.h> #include <linux/module.h> #include <linux/phy/phy.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/reset.h> #include <linux/slab.h> #include <linux/of.h> #include <linux/of_platform.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/phy/phy-cadence.h> #define NUM_SSC_MODE … #define NUM_PHY_TYPE … /* PHY register offsets */ #define SIERRA_COMMON_CDB_OFFSET … #define SIERRA_MACRO_ID_REG … #define SIERRA_CMN_PLLLC_GEN_PREG … #define SIERRA_CMN_PLLLC_FBDIV_INT_MODE0_PREG … #define SIERRA_CMN_PLLLC_DCOCAL_CTRL_PREG … #define SIERRA_CMN_PLLLC_INIT_PREG … #define SIERRA_CMN_PLLLC_ITERTMR_PREG … #define SIERRA_CMN_PLLLC_MODE_PREG … #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG … #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG … #define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG … #define SIERRA_CMN_PLLLC_LOCKSEARCH_PREG … #define SIERRA_CMN_PLLLC_CLK1_PREG … #define SIERRA_CMN_PLLLC_CLK0_PREG … #define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG … #define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG … #define SIERRA_CMN_PLLLC_DSMCORR_PREG … #define SIERRA_CMN_PLLLC_SS_PREG … #define SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG … #define SIERRA_CMN_PLLLC_SSTWOPT_PREG … #define SIERRA_CMN_PLLCSM_PLLEN_TMR_PREG … #define SIERRA_CMN_PLLCSM_PLLPRE_TMR_PREG … #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG … #define SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG … #define SIERRA_SDOSCCAL_CLK_CNT_PREG … #define SIERRA_CMN_REFRCV_PREG … #define SIERRA_CMN_RESCAL_CTRLA_PREG … #define SIERRA_CMN_REFRCV1_PREG … #define SIERRA_CMN_PLLLC1_GEN_PREG … #define SIERRA_CMN_PLLLC1_FBDIV_INT_PREG … #define SIERRA_CMN_PLLLC1_DCOCAL_CTRL_PREG … #define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG … #define SIERRA_CMN_PLLLC1_CLK0_PREG … #define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG … #define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG … #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) … #define SIERRA_DET_STANDEC_A_PREG … #define SIERRA_DET_STANDEC_B_PREG … #define SIERRA_DET_STANDEC_C_PREG … #define SIERRA_DET_STANDEC_D_PREG … #define SIERRA_DET_STANDEC_E_PREG … #define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG … #define SIERRA_PSM_A0IN_TMR_PREG … #define SIERRA_PSM_A3IN_TMR_PREG … #define SIERRA_PSM_DIAG_PREG … #define SIERRA_PSC_LN_A3_PREG … #define SIERRA_PSC_LN_A4_PREG … #define SIERRA_PSC_LN_IDLE_PREG … #define SIERRA_PSC_TX_A0_PREG … #define SIERRA_PSC_TX_A1_PREG … #define SIERRA_PSC_TX_A2_PREG … #define SIERRA_PSC_TX_A3_PREG … #define SIERRA_PSC_RX_A0_PREG … #define SIERRA_PSC_RX_A1_PREG … #define SIERRA_PSC_RX_A2_PREG … #define SIERRA_PSC_RX_A3_PREG … #define SIERRA_PLLCTRL_FBDIV_MODE01_PREG … #define SIERRA_PLLCTRL_SUBRATE_PREG … #define SIERRA_PLLCTRL_GEN_A_PREG … #define SIERRA_PLLCTRL_GEN_D_PREG … #define SIERRA_PLLCTRL_CPGAIN_MODE_PREG … #define SIERRA_PLLCTRL_STATUS_PREG … #define SIERRA_CLKPATH_BIASTRIM_PREG … #define SIERRA_DFE_BIASTRIM_PREG … #define SIERRA_DRVCTRL_ATTEN_PREG … #define SIERRA_DRVCTRL_BOOST_PREG … #define SIERRA_LANE_TX_RECEIVER_DETECT_PREG … #define SIERRA_TX_RCVDET_OVRD_PREG … #define SIERRA_CLKPATHCTRL_TMR_PREG … #define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG … #define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG … #define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG … #define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG … #define SIERRA_CREQ_DCBIASATTEN_OVR_PREG … #define SIERRA_CREQ_CCLKDET_MODE01_PREG … #define SIERRA_RX_CTLE_CAL_PREG … #define SIERRA_RX_CTLE_MAINTENANCE_PREG … #define SIERRA_CREQ_FSMCLK_SEL_PREG … #define SIERRA_CREQ_EQ_CTRL_PREG … #define SIERRA_CREQ_SPARE_PREG … #define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG … #define SIERRA_CTLELUT_CTRL_PREG … #define SIERRA_DEQ_BLK_TAU_CTRL1_PREG … #define SIERRA_DEQ_BLK_TAU_CTRL4_PREG … #define SIERRA_DFE_ECMP_RATESEL_PREG … #define SIERRA_DFE_SMP_RATESEL_PREG … #define SIERRA_DEQ_PHALIGN_CTRL … #define SIERRA_DEQ_CONCUR_CTRL1_PREG … #define SIERRA_DEQ_CONCUR_CTRL2_PREG … #define SIERRA_DEQ_EPIPWR_CTRL2_PREG … #define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG … #define SIERRA_DEQ_ERRCMP_CTRL_PREG … #define SIERRA_DEQ_OFFSET_CTRL_PREG … #define SIERRA_DEQ_GAIN_CTRL_PREG … #define SIERRA_DEQ_VGATUNE_CTRL_PREG … #define SIERRA_DEQ_GLUT0 … #define SIERRA_DEQ_GLUT1 … #define SIERRA_DEQ_GLUT2 … #define SIERRA_DEQ_GLUT3 … #define SIERRA_DEQ_GLUT4 … #define SIERRA_DEQ_GLUT5 … #define SIERRA_DEQ_GLUT6 … #define SIERRA_DEQ_GLUT7 … #define SIERRA_DEQ_GLUT8 … #define SIERRA_DEQ_GLUT9 … #define SIERRA_DEQ_GLUT10 … #define SIERRA_DEQ_GLUT11 … #define SIERRA_DEQ_GLUT12 … #define SIERRA_DEQ_GLUT13 … #define SIERRA_DEQ_GLUT14 … #define SIERRA_DEQ_GLUT15 … #define SIERRA_DEQ_GLUT16 … #define SIERRA_POSTPRECUR_EN_CEPH_CTRL_PREG … #define SIERRA_TAU_EN_CEPH2TO0_PREG … #define SIERRA_TAU_EN_CEPH5TO3_PREG … #define SIERRA_DEQ_ALUT0 … #define SIERRA_DEQ_ALUT1 … #define SIERRA_DEQ_ALUT2 … #define SIERRA_DEQ_ALUT3 … #define SIERRA_DEQ_ALUT4 … #define SIERRA_DEQ_ALUT5 … #define SIERRA_DEQ_ALUT6 … #define SIERRA_DEQ_ALUT7 … #define SIERRA_DEQ_ALUT8 … #define SIERRA_DEQ_ALUT9 … #define SIERRA_DEQ_ALUT10 … #define SIERRA_DEQ_ALUT11 … #define SIERRA_DEQ_ALUT12 … #define SIERRA_DEQ_ALUT13 … #define SIERRA_OEPH_EN_CTRL_PREG … #define SIERRA_DEQ_DFETAP_CTRL_PREG … #define SIERRA_DEQ_DFETAP0 … #define SIERRA_DEQ_DFETAP1 … #define SIERRA_DEQ_DFETAP2 … #define SIERRA_DEQ_DFETAP3 … #define SIERRA_DEQ_DFETAP4 … #define SIERRA_DFE_EN_1010_IGNORE_PREG … #define SIERRA_DEQ_PRECUR_PREG … #define SIERRA_DEQ_POSTCUR_PREG … #define SIERRA_DEQ_POSTCUR_DECR_PREG … #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG … #define SIERRA_DEQ_TAU_CTRL2_PREG … #define SIERRA_DEQ_TAU_CTRL3_PREG … #define SIERRA_DEQ_OPENEYE_CTRL_PREG … #define SIERRA_DEQ_CONCUR_EPIOFFSET_MODE_PREG … #define SIERRA_DEQ_PICTRL_PREG … #define SIERRA_CPICAL_TMRVAL_MODE1_PREG … #define SIERRA_CPICAL_TMRVAL_MODE0_PREG … #define SIERRA_CPICAL_PICNT_MODE1_PREG … #define SIERRA_CPI_OUTBUF_RATESEL_PREG … #define SIERRA_CPI_RESBIAS_BIN_PREG … #define SIERRA_CPI_TRIM_PREG … #define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG … #define SIERRA_CPICAL_RES_STARTCODE_MODE01_PREG … #define SIERRA_EPI_CTRL_PREG … #define SIERRA_LFPSDET_SUPPORT_PREG … #define SIERRA_LFPSFILT_NS_PREG … #define SIERRA_LFPSFILT_RD_PREG … #define SIERRA_LFPSFILT_MP_PREG … #define SIERRA_SIGDET_SUPPORT_PREG … #define SIERRA_SDFILT_H2L_A_PREG … #define SIERRA_SDFILT_L2H_PREG … #define SIERRA_RXBUFFER_CTLECTRL_PREG … #define SIERRA_RXBUFFER_RCDFECTRL_PREG … #define SIERRA_RXBUFFER_DFECTRL_PREG … #define SIERRA_LN_SPARE_REG_PREG … #define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG … #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG … /* PHY PCS common registers */ #define SIERRA_PHY_PCS_COMMON_OFFSET(block_offset) … #define SIERRA_PHY_PIPE_CMN_CTRL1 … #define SIERRA_PHY_PLL_CFG … /* PHY PCS lane registers */ #define SIERRA_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) … #define SIERRA_PHY_ISO_LINK_CTRL … /* PHY PMA common registers */ #define SIERRA_PHY_PMA_COMMON_OFFSET(block_offset) … #define SIERRA_PHY_PMA_CMN_CTRL … /* PHY PMA lane registers */ #define SIERRA_PHY_PMA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) … #define SIERRA_PHY_PMA_XCVR_CTRL … #define SIERRA_MACRO_ID … #define SIERRA_MAX_LANES … #define PLL_LOCK_TIME … #define CDNS_SIERRA_OUTPUT_CLOCKS … #define CDNS_SIERRA_INPUT_CLOCKS … enum cdns_sierra_clock_input { … }; #define SIERRA_NUM_CMN_PLLC … #define SIERRA_NUM_CMN_PLLC_PARENTS … static const struct reg_field macro_id_type = …; static const struct reg_field phy_pll_cfg_1 = …; static const struct reg_field pma_cmn_ready = …; static const struct reg_field pllctrl_lock = …; static const struct reg_field phy_iso_link_ctrl_1 = …; static const struct reg_field cmn_plllc_clk1outdiv_preg = …; static const struct reg_field cmn_plllc_clk1_en_preg = …; static const char * const clk_names[] = …; enum cdns_sierra_cmn_plllc { … }; struct cdns_sierra_pll_mux_reg_fields { … }; static const struct cdns_sierra_pll_mux_reg_fields cmn_plllc_pfdclk1_sel_preg[] = …; struct cdns_sierra_pll_mux { … }; #define to_cdns_sierra_pll_mux(_hw) … #define PLL0_REFCLK_NAME … #define PLL1_REFCLK_NAME … static const struct clk_parent_data pll_mux_parent_data[][SIERRA_NUM_CMN_PLLC_PARENTS] = …; static u32 cdns_sierra_pll_mux_table[][SIERRA_NUM_CMN_PLLC_PARENTS] = …; struct cdns_sierra_derived_refclk { … }; #define to_cdns_sierra_derived_refclk(_hw) … enum cdns_sierra_phy_type { … }; enum cdns_sierra_ssc_mode { … }; struct cdns_sierra_inst { … }; struct cdns_reg_pairs { … }; struct cdns_sierra_vals { … }; struct cdns_sierra_data { … }; struct cdns_regmap_cdb_context { … }; struct cdns_sierra_phy { … }; static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val) { … } static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val) { … } #define SIERRA_LANE_CDB_REGMAP_CONF(n) … static const struct regmap_config cdns_sierra_lane_cdb_config[] = …; static const struct regmap_config cdns_sierra_common_cdb_config = …; static const struct regmap_config cdns_sierra_phy_pcs_cmn_cdb_config = …; #define SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF(n) … static const struct regmap_config cdns_sierra_phy_pcs_lane_cdb_config[] = …; static const struct regmap_config cdns_sierra_phy_pma_cmn_cdb_config = …; #define SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF(n) … static const struct regmap_config cdns_sierra_phy_pma_lane_cdb_config[] = …; static int cdns_sierra_phy_init(struct phy *gphy) { … } static int cdns_sierra_phy_on(struct phy *gphy) { … } static int cdns_sierra_phy_off(struct phy *gphy) { … } static int cdns_sierra_phy_reset(struct phy *gphy) { struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent); reset_control_assert(sp->phy_rst); reset_control_deassert(sp->phy_rst); return 0; }; static const struct phy_ops ops = …; static int cdns_sierra_noop_phy_on(struct phy *gphy) { … } static const struct phy_ops noop_ops = …; static u8 cdns_sierra_pll_mux_get_parent(struct clk_hw *hw) { … } static int cdns_sierra_pll_mux_set_parent(struct clk_hw *hw, u8 index) { … } static const struct clk_ops cdns_sierra_pll_mux_ops = …; static int cdns_sierra_pll_mux_register(struct cdns_sierra_phy *sp, struct regmap_field *pfdclk1_sel_field, struct regmap_field *plllc1en_field, struct regmap_field *termen_field, int clk_index) { … } static int cdns_sierra_phy_register_pll_mux(struct cdns_sierra_phy *sp) { … } static int cdns_sierra_derived_refclk_enable(struct clk_hw *hw) { … } static void cdns_sierra_derived_refclk_disable(struct clk_hw *hw) { … } static int cdns_sierra_derived_refclk_is_enabled(struct clk_hw *hw) { … } static const struct clk_ops cdns_sierra_derived_refclk_ops = …; static int cdns_sierra_derived_refclk_register(struct cdns_sierra_phy *sp) { … } static void cdns_sierra_clk_unregister(struct cdns_sierra_phy *sp) { … } static int cdns_sierra_clk_register(struct cdns_sierra_phy *sp) { … } static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, struct device_node *child) { … } static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base, u32 block_offset, u8 reg_offset_shift, const struct regmap_config *config) { … } static int cdns_regfield_init(struct cdns_sierra_phy *sp) { … } static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp, void __iomem *base, u8 block_offset_shift, u8 reg_offset_shift) { … } static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, struct device *dev) { … } static int cdns_sierra_phy_clk(struct cdns_sierra_phy *sp) { … } static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp) { … } static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp) { … } static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp, struct device *dev) { … } static int cdns_sierra_phy_configure_multilink(struct cdns_sierra_phy *sp) { … } static int cdns_sierra_phy_probe(struct platform_device *pdev) { … } static void cdns_sierra_phy_remove(struct platform_device *pdev) { … } /* SGMII PHY PMA lane configuration */ static struct cdns_reg_pairs sgmii_phy_pma_ln_regs[] = …; static struct cdns_sierra_vals sgmii_phy_pma_ln_vals = …; /* SGMII refclk 100MHz, no ssc, opt3 and GE1 links using PLL LC1 */ static const struct cdns_reg_pairs sgmii_100_no_ssc_plllc1_opt3_cmn_regs[] = …; static const struct cdns_reg_pairs sgmii_100_no_ssc_plllc1_opt3_ln_regs[] = …; static struct cdns_sierra_vals sgmii_100_no_ssc_plllc1_opt3_cmn_vals = …; static struct cdns_sierra_vals sgmii_100_no_ssc_plllc1_opt3_ln_vals = …; /* QSGMII PHY PMA lane configuration */ static struct cdns_reg_pairs qsgmii_phy_pma_ln_regs[] = …; static struct cdns_sierra_vals qsgmii_phy_pma_ln_vals = …; /* QSGMII refclk 100MHz, 20b, opt1, No BW cal, no ssc, PLL LC1 */ static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_cmn_regs[] = …; static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_ln_regs[] = …; static struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_cmn_vals = …; static struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_ln_vals = …; /* PCIE PHY PCS common configuration */ static struct cdns_reg_pairs pcie_phy_pcs_cmn_regs[] = …; static struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = …; /* refclk100MHz_32b_PCIe_cmn_pll_no_ssc, pcie_links_using_plllc, pipe_bw_3 */ static const struct cdns_reg_pairs pcie_100_no_ssc_plllc_cmn_regs[] = …; /* * refclk100MHz_32b_PCIe_ln_no_ssc, multilink, using_plllc, * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz */ static const struct cdns_reg_pairs ml_pcie_100_no_ssc_ln_regs[] = …; static struct cdns_sierra_vals pcie_100_no_ssc_plllc_cmn_vals = …; static struct cdns_sierra_vals ml_pcie_100_no_ssc_ln_vals = …; /* * TI J721E: * refclk100MHz_32b_PCIe_ln_no_ssc, multilink, using_plllc, * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz */ static const struct cdns_reg_pairs ti_ml_pcie_100_no_ssc_ln_regs[] = …; static struct cdns_sierra_vals ti_ml_pcie_100_no_ssc_ln_vals = …; /* refclk100MHz_32b_PCIe_cmn_pll_int_ssc, pcie_links_using_plllc, pipe_bw_3 */ static const struct cdns_reg_pairs pcie_100_int_ssc_plllc_cmn_regs[] = …; /* * refclk100MHz_32b_PCIe_ln_int_ssc, multilink, using_plllc, * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz */ static const struct cdns_reg_pairs ml_pcie_100_int_ssc_ln_regs[] = …; static struct cdns_sierra_vals pcie_100_int_ssc_plllc_cmn_vals = …; static struct cdns_sierra_vals ml_pcie_100_int_ssc_ln_vals = …; /* * TI J721E: * refclk100MHz_32b_PCIe_ln_int_ssc, multilink, using_plllc, * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz */ static const struct cdns_reg_pairs ti_ml_pcie_100_int_ssc_ln_regs[] = …; static struct cdns_sierra_vals ti_ml_pcie_100_int_ssc_ln_vals = …; /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc, pcie_links_using_plllc, pipe_bw_3 */ static const struct cdns_reg_pairs pcie_100_ext_ssc_plllc_cmn_regs[] = …; /* * refclk100MHz_32b_PCIe_ln_ext_ssc, multilink, using_plllc, * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz */ static const struct cdns_reg_pairs ml_pcie_100_ext_ssc_ln_regs[] = …; static struct cdns_sierra_vals pcie_100_ext_ssc_plllc_cmn_vals = …; static struct cdns_sierra_vals ml_pcie_100_ext_ssc_ln_vals = …; /* * TI J721E: * refclk100MHz_32b_PCIe_ln_ext_ssc, multilink, using_plllc, * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz */ static const struct cdns_reg_pairs ti_ml_pcie_100_ext_ssc_ln_regs[] = …; static struct cdns_sierra_vals ti_ml_pcie_100_ext_ssc_ln_vals = …; /* refclk100MHz_32b_PCIe_cmn_pll_no_ssc */ static const struct cdns_reg_pairs cdns_pcie_cmn_regs_no_ssc[] = …; /* refclk100MHz_32b_PCIe_ln_no_ssc */ static const struct cdns_reg_pairs cdns_pcie_ln_regs_no_ssc[] = …; static struct cdns_sierra_vals pcie_100_no_ssc_cmn_vals = …; static struct cdns_sierra_vals pcie_100_no_ssc_ln_vals = …; /* refclk100MHz_32b_PCIe_cmn_pll_int_ssc */ static const struct cdns_reg_pairs cdns_pcie_cmn_regs_int_ssc[] = …; /* refclk100MHz_32b_PCIe_ln_int_ssc */ static const struct cdns_reg_pairs cdns_pcie_ln_regs_int_ssc[] = …; static struct cdns_sierra_vals pcie_100_int_ssc_cmn_vals = …; static struct cdns_sierra_vals pcie_100_int_ssc_ln_vals = …; /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */ static const struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = …; /* refclk100MHz_32b_PCIe_ln_ext_ssc */ static const struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = …; static struct cdns_sierra_vals pcie_100_ext_ssc_cmn_vals = …; static struct cdns_sierra_vals pcie_100_ext_ssc_ln_vals = …; /* refclk100MHz_20b_USB_cmn_pll_ext_ssc */ static const struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = …; /* refclk100MHz_20b_USB_ln_ext_ssc */ static const struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = …; static struct cdns_sierra_vals usb_100_ext_ssc_cmn_vals = …; static struct cdns_sierra_vals usb_100_ext_ssc_ln_vals = …; /* SGMII PHY common configuration */ static const struct cdns_reg_pairs sgmii_pma_cmn_vals[] = …; static struct cdns_sierra_vals sgmii_cmn_vals = …; /* SGMII PHY lane configuration */ static const struct cdns_reg_pairs sgmii_ln_regs[] = …; static struct cdns_sierra_vals sgmii_pma_ln_vals = …; static const struct cdns_sierra_data cdns_map_sierra = …; static const struct cdns_sierra_data cdns_ti_map_sierra = …; static const struct of_device_id cdns_sierra_id_table[] = …; MODULE_DEVICE_TABLE(of, cdns_sierra_id_table); static struct platform_driver cdns_sierra_driver = …; module_platform_driver(…) …; MODULE_ALIAS(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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