// SPDX-License-Identifier: GPL-2.0 /* * PCIe phy driver for Kirin 970 * * Copyright (C) 2017 HiSilicon Electronics Co., Ltd. * https://www.huawei.com * Copyright (C) 2021 Huawei Technologies Co., Ltd. * https://www.huawei.com * * Authors: * Mauro Carvalho Chehab <[email protected]> * Manivannan Sadhasivam <[email protected]> * * Based on: * https://lore.kernel.org/lkml/4c9d6581478aa966698758c0420933f5defab4dd.1612335031.git.mchehab+huawei@kernel.org/ */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/gpio.h> #include <linux/kernel.h> #include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/of_gpio.h> #include <linux/phy/phy.h> #include <linux/platform_device.h> #include <linux/regmap.h> #define AXI_CLK_FREQ … #define REF_CLK_FREQ … /* PCIe CTRL registers */ #define SOC_PCIECTRL_CTRL7_ADDR … #define SOC_PCIECTRL_CTRL12_ADDR … #define SOC_PCIECTRL_CTRL20_ADDR … #define SOC_PCIECTRL_CTRL21_ADDR … #define PCIE_OUTPUT_PULL_BITS … #define SOC_PCIECTRL_CTRL20_2P_MEM_CTRL … #define SOC_PCIECTRL_CTRL21_DEFAULT … #define PCIE_PULL_UP_SYS_AUX_PWR_DET … #define PCIE_OUTPUT_PULL_DOWN … /* PCIe PHY registers */ #define SOC_PCIEPHY_CTRL0_ADDR … #define SOC_PCIEPHY_CTRL1_ADDR … #define SOC_PCIEPHY_CTRL38_ADDR … #define SOC_PCIEPHY_STATE0_ADDR … #define RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1 … #define SUP_DIG_LVL_OVRD_IN … #define LANEN_DIG_ASIC_TX_OVRD_IN_1 … #define LANEN_DIG_ASIC_TX_OVRD_IN_2 … #define PCIEPHY_RESET_BIT … #define PCIEPHY_PIPE_LINE0_RESET_BIT … #define PCIE_TXDETECT_RX_FAIL … #define PCIE_CLK_SOURCE … #define PCIE_IS_CLOCK_STABLE … #define PCIE_PULL_DOWN_PHY_TEST_POWERDOWN … #define PCIE_DEASSERT_CONTROLLER_PERST … #define EYEPARAM_NOCFG … #define EYE_PARM0_MASK … #define EYE_PARM1_MASK … #define EYE_PARM2_MASK … #define EYE_PARM3_MASK … #define EYE_PARM4_MASK … #define EYE_PARM0_EN … #define EYE_PARM1_EN … #define EYE_PARM2_EN … #define EYE_PARM3_EN … #define EYE_PARM4_EN … /* hi3670 pciephy register */ #define APB_PHY_START_ADDR … #define SOC_PCIEPHY_MMC1PLL_CTRL1 … #define SOC_PCIEPHY_MMC1PLL_CTRL16 … #define SOC_PCIEPHY_MMC1PLL_CTRL17 … #define SOC_PCIEPHY_MMC1PLL_CTRL20 … #define SOC_PCIEPHY_MMC1PLL_CTRL21 … #define SOC_PCIEPHY_MMC1PLL_STAT0 … #define CRGPERIPH_PEREN12 … #define CRGPERIPH_PERDIS12 … #define CRGPERIPH_PCIECTRL0 … #define PCIE_FNPLL_FBDIV_MASK … #define PCIE_FNPLL_FRACDIV_MASK … #define PCIE_FNPLL_POSTDIV1_MASK … #define PCIE_FNPLL_POSTDIV2_MASK … #define PCIE_FNPLL_PLL_MODE_MASK … #define PCIE_FNPLL_DLL_EN … #define PCIE_FNPLL_FBDIV … #define PCIE_FNPLL_FRACDIV … #define PCIE_FNPLL_POSTDIV1 … #define PCIE_FNPLL_POSTDIV2 … #define PCIE_FNPLL_PLL_MODE … #define PCIE_PHY_MMC1PLL … #define PCIE_PHY_CHOOSE_FNPLL … #define PCIE_PHY_MMC1PLL_DISABLE … #define PCIE_PHY_PCIEPL_BP … /* define ie,oe cfg */ #define IO_OE_HARD_GT_MODE … #define IO_IE_EN_HARD_BYPASS … #define IO_OE_EN_HARD_BYPASS … #define IO_HARD_CTRL_DEBOUNCE_BYPASS … #define IO_OE_GT_MODE … #define DEBOUNCE_WAITCFG_IN … #define DEBOUNCE_WAITCFG_OUT … #define IO_HP_DEBOUNCE_GT … #define IO_PHYREF_SOFT_GT_MODE … #define IO_REF_SOFT_GT_MODE … #define IO_REF_HARD_GT_MODE … /* noc power domain */ #define NOC_POWER_IDLEREQ_1 … #define NOC_POWER_IDLE_1 … #define NOC_PW_MASK … #define NOC_PW_SET_BIT … #define NUM_EYEPARAM … /* info located in sysctrl */ #define SCTRL_PCIE_CMOS_OFFSET … #define SCTRL_PCIE_CMOS_BIT … #define SCTRL_PCIE_ISO_OFFSET … #define SCTRL_PCIE_ISO_BIT … #define SCTRL_PCIE_HPCLK_OFFSET … #define SCTRL_PCIE_HPCLK_BIT … #define SCTRL_PCIE_OE_OFFSET … #define PCIE_DEBOUNCE_PARAM … #define PCIE_OE_BYPASS … /* peri_crg ctrl */ #define CRGCTRL_PCIE_ASSERT_OFFSET … #define CRGCTRL_PCIE_ASSERT_BIT … #define FNPLL_HAS_LOCKED … /* Time for delay */ #define TIME_CMOS_MIN … #define TIME_CMOS_MAX … #define PIPE_CLK_STABLE_TIME … #define PLL_CTRL_WAIT_TIME … #define NOC_POWER_TIME … struct hi3670_pcie_phy { … }; /* Registers in PCIePHY */ static inline void hi3670_apb_phy_writel(struct hi3670_pcie_phy *phy, u32 val, u32 reg) { … } static inline u32 hi3670_apb_phy_readl(struct hi3670_pcie_phy *phy, u32 reg) { … } static inline void hi3670_apb_phy_updatel(struct hi3670_pcie_phy *phy, u32 val, u32 mask, u32 reg) { … } static inline void kirin_apb_natural_phy_writel(struct hi3670_pcie_phy *phy, u32 val, u32 reg) { … } static inline u32 kirin_apb_natural_phy_readl(struct hi3670_pcie_phy *phy, u32 reg) { … } static void hi3670_pcie_phy_oe_enable(struct hi3670_pcie_phy *phy, bool enable) { … } static void hi3670_pcie_get_eyeparam(struct hi3670_pcie_phy *phy) { … } static void hi3670_pcie_set_eyeparam(struct hi3670_pcie_phy *phy) { … } static void hi3670_pcie_natural_cfg(struct hi3670_pcie_phy *phy) { … } static void hi3670_pcie_pll_init(struct hi3670_pcie_phy *phy) { … } static int hi3670_pcie_pll_ctrl(struct hi3670_pcie_phy *phy, bool enable) { … } static void hi3670_pcie_hp_debounce_gt(struct hi3670_pcie_phy *phy, bool open) { … } static void hi3670_pcie_phyref_gt(struct hi3670_pcie_phy *phy, bool open) { … } static void hi3670_pcie_oe_ctrl(struct hi3670_pcie_phy *phy, bool en_flag) { … } static void hi3670_pcie_ioref_gt(struct hi3670_pcie_phy *phy, bool open) { … } static int hi3670_pcie_allclk_ctrl(struct hi3670_pcie_phy *phy, bool clk_on) { … } static bool is_pipe_clk_stable(struct hi3670_pcie_phy *phy) { … } static int hi3670_pcie_noc_power(struct hi3670_pcie_phy *phy, bool enable) { … } static int hi3670_pcie_get_resources_from_pcie(struct hi3670_pcie_phy *phy) { … } static int kirin_pcie_clk_ctrl(struct hi3670_pcie_phy *phy, bool enable) { … } static int hi3670_pcie_phy_init(struct phy *generic_phy) { … } static int hi3670_pcie_phy_power_on(struct phy *generic_phy) { … } static int hi3670_pcie_phy_power_off(struct phy *generic_phy) { … } static const struct phy_ops hi3670_phy_ops = …; static int hi3670_pcie_phy_get_resources(struct hi3670_pcie_phy *phy, struct platform_device *pdev) { … } static int hi3670_pcie_phy_probe(struct platform_device *pdev) { … } static const struct of_device_id hi3670_pcie_phy_match[] = …; static struct platform_driver hi3670_pcie_phy_driver = …; builtin_platform_driver(…) …; MODULE_DEVICE_TABLE(of, hi3670_pcie_phy_match); MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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