// SPDX-License-Identifier: GPL-2.0-only /* * PCIe PHY driver for Lantiq VRX200 and ARX300 SoCs. * * Copyright (C) 2019 Martin Blumenstingl <[email protected]> * * Based on the BSP (called "UGW") driver: * Copyright (C) 2009-2015 Lei Chuanhua <[email protected]> * Copyright (C) 2016 Intel Corporation * * TODO: PHY modes other than 36MHz (without "SSC") */ #include <linux/bitfield.h> #include <linux/bits.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/of.h> #include <linux/phy/phy.h> #include <linux/platform_device.h> #include <linux/property.h> #include <linux/regmap.h> #include <linux/reset.h> #include <dt-bindings/phy/phy-lantiq-vrx200-pcie.h> #define PCIE_PHY_PLL_CTRL1 … #define PCIE_PHY_PLL_CTRL2 … #define PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK … #define PCIE_PHY_PLL_CTRL2_CONST_SDM_EN … #define PCIE_PHY_PLL_CTRL2_PLL_SDM_EN … #define PCIE_PHY_PLL_CTRL3 … #define PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN … #define PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK … #define PCIE_PHY_PLL_CTRL4 … #define PCIE_PHY_PLL_CTRL5 … #define PCIE_PHY_PLL_CTRL6 … #define PCIE_PHY_PLL_CTRL7 … #define PCIE_PHY_PLL_A_CTRL1 … #define PCIE_PHY_PLL_A_CTRL2 … #define PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN … #define PCIE_PHY_PLL_A_CTRL3 … #define PCIE_PHY_PLL_A_CTRL3_MMD_MASK … #define PCIE_PHY_PLL_STATUS … #define PCIE_PHY_TX1_CTRL1 … #define PCIE_PHY_TX1_CTRL1_FORCE_EN … #define PCIE_PHY_TX1_CTRL1_LOAD_EN … #define PCIE_PHY_TX1_CTRL2 … #define PCIE_PHY_TX1_CTRL3 … #define PCIE_PHY_TX1_A_CTRL1 … #define PCIE_PHY_TX1_A_CTRL2 … #define PCIE_PHY_TX1_MOD1 … #define PCIE_PHY_TX1_MOD2 … #define PCIE_PHY_TX1_MOD3 … #define PCIE_PHY_TX2_CTRL1 … #define PCIE_PHY_TX2_CTRL1_LOAD_EN … #define PCIE_PHY_TX2_CTRL2 … #define PCIE_PHY_TX2_A_CTRL1 … #define PCIE_PHY_TX2_A_CTRL2 … #define PCIE_PHY_TX2_MOD1 … #define PCIE_PHY_TX2_MOD2 … #define PCIE_PHY_TX2_MOD3 … #define PCIE_PHY_RX1_CTRL1 … #define PCIE_PHY_RX1_CTRL1_LOAD_EN … #define PCIE_PHY_RX1_CTRL2 … #define PCIE_PHY_RX1_CDR … #define PCIE_PHY_RX1_EI … #define PCIE_PHY_RX1_A_CTRL … struct ltq_vrx200_pcie_phy_priv { … }; static void ltq_vrx200_pcie_phy_common_setup(struct phy *phy) { … } static void pcie_phy_36mhz_mode_setup(struct phy *phy) { … } static int ltq_vrx200_pcie_phy_wait_for_pll(struct phy *phy) { … } static void ltq_vrx200_pcie_phy_apply_workarounds(struct phy *phy) { … } static int ltq_vrx200_pcie_phy_init(struct phy *phy) { … } static int ltq_vrx200_pcie_phy_exit(struct phy *phy) { … } static int ltq_vrx200_pcie_phy_power_on(struct phy *phy) { … } static int ltq_vrx200_pcie_phy_power_off(struct phy *phy) { … } static const struct phy_ops ltq_vrx200_pcie_phy_ops = …; static struct phy *ltq_vrx200_pcie_phy_xlate(struct device *dev, const struct of_phandle_args *args) { … } static int ltq_vrx200_pcie_phy_probe(struct platform_device *pdev) { … } static const struct of_device_id ltq_vrx200_pcie_phy_of_match[] = …; MODULE_DEVICE_TABLE(of, ltq_vrx200_pcie_phy_of_match); static struct platform_driver ltq_vrx200_pcie_phy_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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