// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2015 Linaro, Ltd. * Rob Herring <[email protected]> * * Based on vendor driver: * Copyright (C) 2013 Marvell Inc. * Author: Chao Xie <[email protected]> */ #include <linux/delay.h> #include <linux/slab.h> #include <linux/of.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/err.h> #include <linux/clk.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/phy/phy.h> /* USB PXA1928 PHY mapping */ #define PHY_28NM_PLL_REG0 … #define PHY_28NM_PLL_REG1 … #define PHY_28NM_CAL_REG … #define PHY_28NM_TX_REG0 … #define PHY_28NM_TX_REG1 … #define PHY_28NM_RX_REG0 … #define PHY_28NM_RX_REG1 … #define PHY_28NM_DIG_REG0 … #define PHY_28NM_DIG_REG1 … #define PHY_28NM_TEST_REG0 … #define PHY_28NM_TEST_REG1 … #define PHY_28NM_MOC_REG … #define PHY_28NM_PHY_RESERVE … #define PHY_28NM_OTG_REG … #define PHY_28NM_CHRG_DET … #define PHY_28NM_CTRL_REG0 … #define PHY_28NM_CTRL_REG1 … #define PHY_28NM_CTRL_REG2 … #define PHY_28NM_CTRL_REG3 … /* PHY_28NM_PLL_REG0 */ #define PHY_28NM_PLL_READY … #define PHY_28NM_PLL_SELLPFR_SHIFT … #define PHY_28NM_PLL_SELLPFR_MASK … #define PHY_28NM_PLL_FBDIV_SHIFT … #define PHY_28NM_PLL_FBDIV_MASK … #define PHY_28NM_PLL_ICP_SHIFT … #define PHY_28NM_PLL_ICP_MASK … #define PHY_28NM_PLL_REFDIV_SHIFT … #define PHY_28NM_PLL_REFDIV_MASK … /* PHY_28NM_PLL_REG1 */ #define PHY_28NM_PLL_PU_BY_REG … #define PHY_28NM_PLL_PU_PLL … /* PHY_28NM_CAL_REG */ #define PHY_28NM_PLL_PLLCAL_DONE … #define PHY_28NM_PLL_IMPCAL_DONE … #define PHY_28NM_PLL_KVCO_SHIFT … #define PHY_28NM_PLL_KVCO_MASK … #define PHY_28NM_PLL_CAL12_SHIFT … #define PHY_28NM_PLL_CAL12_MASK … #define PHY_28NM_IMPCAL_VTH_SHIFT … #define PHY_28NM_IMPCAL_VTH_MASK … #define PHY_28NM_PLLCAL_START_SHIFT … #define PHY_28NM_IMPCAL_START_SHIFT … /* PHY_28NM_TX_REG0 */ #define PHY_28NM_TX_PU_BY_REG … #define PHY_28NM_TX_PU_ANA … #define PHY_28NM_TX_AMP_SHIFT … #define PHY_28NM_TX_AMP_MASK … /* PHY_28NM_RX_REG0 */ #define PHY_28NM_RX_SQ_THRESH_SHIFT … #define PHY_28NM_RX_SQ_THRESH_MASK … /* PHY_28NM_RX_REG1 */ #define PHY_28NM_RX_SQCAL_DONE … /* PHY_28NM_DIG_REG0 */ #define PHY_28NM_DIG_BITSTAFFING_ERR … #define PHY_28NM_DIG_SYNC_ERR … #define PHY_28NM_DIG_SQ_FILT_SHIFT … #define PHY_28NM_DIG_SQ_FILT_MASK … #define PHY_28NM_DIG_SQ_BLK_SHIFT … #define PHY_28NM_DIG_SQ_BLK_MASK … #define PHY_28NM_DIG_SYNC_NUM_SHIFT … #define PHY_28NM_DIG_SYNC_NUM_MASK … #define PHY_28NM_PLL_LOCK_BYPASS … /* PHY_28NM_OTG_REG */ #define PHY_28NM_OTG_CONTROL_BY_PIN … #define PHY_28NM_OTG_PU_OTG … #define PHY_28NM_CHGDTC_ENABLE_SWITCH_DM_SHIFT_28 … #define PHY_28NM_CHGDTC_ENABLE_SWITCH_DP_SHIFT_28 … #define PHY_28NM_CHGDTC_VSRC_CHARGE_SHIFT_28 … #define PHY_28NM_CHGDTC_VDAT_CHARGE_SHIFT_28 … #define PHY_28NM_CHGDTC_CDP_DM_AUTO_SWITCH_SHIFT_28 … #define PHY_28NM_CHGDTC_DP_DM_SWAP_SHIFT_28 … #define PHY_28NM_CHGDTC_PU_CHRG_DTC_SHIFT_28 … #define PHY_28NM_CHGDTC_PD_EN_SHIFT_28 … #define PHY_28NM_CHGDTC_DCP_EN_SHIFT_28 … #define PHY_28NM_CHGDTC_CDP_EN_SHIFT_28 … #define PHY_28NM_CHGDTC_TESTMON_CHRGDTC_SHIFT_28 … #define PHY_28NM_CTRL1_CHRG_DTC_OUT_SHIFT_28 … #define PHY_28NM_CTRL1_VBUSDTC_OUT_SHIFT_28 … #define PHY_28NM_CTRL3_OVERWRITE … #define PHY_28NM_CTRL3_VBUS_VALID … #define PHY_28NM_CTRL3_AVALID … #define PHY_28NM_CTRL3_BVALID … struct mv_usb2_phy { … }; static int wait_for_reg(void __iomem *reg, u32 mask, u32 ms) { … } static int mv_usb2_phy_28nm_init(struct phy *phy) { … } static int mv_usb2_phy_28nm_power_on(struct phy *phy) { … } static int mv_usb2_phy_28nm_power_off(struct phy *phy) { … } static int mv_usb2_phy_28nm_exit(struct phy *phy) { … } static const struct phy_ops usb_ops = …; static int mv_usb2_phy_probe(struct platform_device *pdev) { … } static const struct of_device_id mv_usbphy_dt_match[] = …; MODULE_DEVICE_TABLE(of, mv_usbphy_dt_match); static struct platform_driver mv_usb2_phy_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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