// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2015 MediaTek Inc. * Author: Chunfeng Yun <[email protected]> * */ #include <dt-bindings/phy/phy.h> #include <linux/clk.h> #include <linux/debugfs.h> #include <linux/delay.h> #include <linux/iopoll.h> #include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/nvmem-consumer.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/phy/phy.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include "phy-mtk-io.h" /* version V1 sub-banks offset base address */ /* banks shared by multiple phys */ #define SSUSB_SIFSLV_V1_SPLLC … #define SSUSB_SIFSLV_V1_U2FREQ … #define SSUSB_SIFSLV_V1_CHIP … /* u2 phy bank */ #define SSUSB_SIFSLV_V1_U2PHY_COM … /* u3/pcie/sata phy banks */ #define SSUSB_SIFSLV_V1_U3PHYD … #define SSUSB_SIFSLV_V1_U3PHYA … /* version V2/V3 sub-banks offset base address */ /* V3: U2FREQ is not used anymore, but reserved */ /* u2 phy banks */ #define SSUSB_SIFSLV_V2_MISC … #define SSUSB_SIFSLV_V2_U2FREQ … #define SSUSB_SIFSLV_V2_U2PHY_COM … /* u3/pcie/sata phy banks */ #define SSUSB_SIFSLV_V2_SPLLC … #define SSUSB_SIFSLV_V2_CHIP … #define SSUSB_SIFSLV_V2_U3PHYD … #define SSUSB_SIFSLV_V2_U3PHYA … #define U3P_MISC_REG1 … #define MR1_EFUSE_AUTO_LOAD_DIS … #define U3P_USBPHYACR0 … #define PA0_RG_U2PLL_FORCE_ON … #define PA0_USB20_PLL_PREDIV … #define PA0_RG_USB20_INTR_EN … #define U3P_USBPHYACR1 … #define PA1_RG_INTR_CAL … #define PA1_RG_VRT_SEL … #define PA1_RG_TERM_SEL … #define U3P_USBPHYACR2 … #define PA2_RG_U2PLL_BW … #define PA2_RG_SIF_U2PLL_FORCE_EN … #define U3P_USBPHYACR5 … #define PA5_RG_U2_HSTX_SRCAL_EN … #define PA5_RG_U2_HSTX_SRCTRL … #define PA5_RG_U2_HS_100U_U3_EN … #define U3P_USBPHYACR6 … #define PA6_RG_U2_PRE_EMP … #define PA6_RG_U2_BC11_SW_EN … #define PA6_RG_U2_OTG_VBUSCMP_EN … #define PA6_RG_U2_DISCTH … #define PA6_RG_U2_SQTH … #define U3P_U2PHYACR4 … #define P2C_RG_USB20_GPIO_CTL … #define P2C_USB20_GPIO_MODE … #define P2C_U2_GPIO_CTR_MSK … #define U3P_U2PHYA_RESV … #define P2R_RG_U2PLL_FBDIV_26M … #define P2R_RG_U2PLL_FBDIV_48M … #define U3P_U2PHYA_RESV1 … #define P2R_RG_U2PLL_REFCLK_SEL … #define P2R_RG_U2PLL_FRA_EN … #define U3D_U2PHYDCR0 … #define P2C_RG_SIF_U2PLL_FORCE_ON … #define U3P_U2PHYDTM0 … #define P2C_FORCE_UART_EN … #define P2C_FORCE_DATAIN … #define P2C_FORCE_DM_PULLDOWN … #define P2C_FORCE_DP_PULLDOWN … #define P2C_FORCE_XCVRSEL … #define P2C_FORCE_SUSPENDM … #define P2C_FORCE_TERMSEL … #define P2C_RG_DATAIN … #define P2C_RG_DMPULLDOWN … #define P2C_RG_DPPULLDOWN … #define P2C_RG_XCVRSEL … #define P2C_RG_SUSPENDM … #define P2C_RG_TERMSEL … #define P2C_DTM0_PART_MASK … #define U3P_U2PHYDTM1 … #define P2C_RG_UART_EN … #define P2C_FORCE_IDDIG … #define P2C_RG_VBUSVALID … #define P2C_RG_SESSEND … #define P2C_RG_AVALID … #define P2C_RG_IDDIG … #define U3P_U2PHYBC12C … #define P2C_RG_CHGDT_EN … #define U3P_U3_CHIP_GPIO_CTLD … #define P3C_REG_IP_SW_RST … #define P3C_MCU_BUS_CK_GATE_EN … #define P3C_FORCE_IP_SW_RST … #define U3P_U3_CHIP_GPIO_CTLE … #define P3C_RG_SWRST_U3_PHYD … #define P3C_RG_SWRST_U3_PHYD_FORCE_EN … #define U3P_U3_PHYA_REG0 … #define P3A_RG_IEXT_INTR … #define P3A_RG_CLKDRV_OFF … #define U3P_U3_PHYA_REG1 … #define P3A_RG_CLKDRV_AMP … #define U3P_U3_PHYA_REG6 … #define P3A_RG_TX_EIDLE_CM … #define U3P_U3_PHYA_REG9 … #define P3A_RG_RX_DAC_MUX … #define U3P_U3_PHYA_DA_REG0 … #define P3A_RG_XTAL_EXT_PE2H … #define P3A_RG_XTAL_EXT_PE1H … #define P3A_RG_XTAL_EXT_EN_U3 … #define U3P_U3_PHYA_DA_REG4 … #define P3A_RG_PLL_DIVEN_PE2H … #define P3A_RG_PLL_BC_PE2H … #define U3P_U3_PHYA_DA_REG5 … #define P3A_RG_PLL_BR_PE2H … #define P3A_RG_PLL_IC_PE2H … #define U3P_U3_PHYA_DA_REG6 … #define P3A_RG_PLL_IR_PE2H … #define U3P_U3_PHYA_DA_REG7 … #define P3A_RG_PLL_BP_PE2H … #define U3P_U3_PHYA_DA_REG20 … #define P3A_RG_PLL_DELTA1_PE2H … #define U3P_U3_PHYA_DA_REG25 … #define P3A_RG_PLL_DELTA_PE2H … #define U3P_U3_PHYD_LFPS1 … #define P3D_RG_FWAKE_TH … #define U3P_U3_PHYD_IMPCAL0 … #define P3D_RG_FORCE_TX_IMPEL … #define P3D_RG_TX_IMPEL … #define U3P_U3_PHYD_IMPCAL1 … #define P3D_RG_FORCE_RX_IMPEL … #define P3D_RG_RX_IMPEL … #define U3P_U3_PHYD_RSV … #define P3D_RG_EFUSE_AUTO_LOAD_DIS … #define U3P_U3_PHYD_CDR1 … #define P3D_RG_CDR_BIR_LTD1 … #define P3D_RG_CDR_BIR_LTD0 … #define U3P_U3_PHYD_TOP1 … #define P3D_RG_PHY_MODE … #define P3D_RG_FORCE_PHY_MODE … #define U3P_U3_PHYD_RXDET1 … #define P3D_RG_RXDET_STB2_SET … #define U3P_U3_PHYD_RXDET2 … #define P3D_RG_RXDET_STB2_SET_P3 … #define U3P_SPLLC_XTALCTL3 … #define XC3_RG_U3_XTAL_RX_PWD … #define XC3_RG_U3_FRC_XTAL_RX_PWD … #define U3P_U2FREQ_FMCR0 … #define P2F_RG_MONCLK_SEL … #define P2F_RG_FREQDET_EN … #define P2F_RG_CYCLECNT … #define U3P_U2FREQ_VALUE … #define U3P_U2FREQ_FMMONR1 … #define P2F_USB_FM_VALID … #define P2F_RG_FRCK_EN … #define U3P_REF_CLK … #define U3P_SLEW_RATE_COEF … #define U3P_SR_COEF_DIVISOR … #define U3P_FM_DET_CYCLE_CNT … /* SATA register setting */ #define PHYD_CTRL_SIGNAL_MODE4 … /* CDR Charge Pump P-path current adjustment */ #define RG_CDR_BICLTD1_GEN1_MSK … #define RG_CDR_BICLTD0_GEN1_MSK … #define PHYD_DESIGN_OPTION2 … /* Symbol lock count selection */ #define RG_LOCK_CNT_SEL_MSK … #define PHYD_DESIGN_OPTION9 … /* COMWAK GAP width window */ #define RG_TG_MAX_MSK … /* COMINIT GAP width window */ #define RG_T2_MAX_MSK … /* COMWAK GAP width window */ #define RG_TG_MIN_MSK … /* COMINIT GAP width window */ #define RG_T2_MIN_MSK … #define ANA_RG_CTRL_SIGNAL1 … /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */ #define RG_IDRV_0DB_GEN1_MSK … #define ANA_RG_CTRL_SIGNAL4 … #define RG_CDR_BICLTR_GEN1_MSK … /* Loop filter R1 resistance adjustment for Gen1 speed */ #define RG_CDR_BR_GEN2_MSK … #define ANA_RG_CTRL_SIGNAL6 … /* I-path capacitance adjustment for Gen1 */ #define RG_CDR_BC_GEN1_MSK … #define RG_CDR_BIRLTR_GEN1_MSK … #define ANA_EQ_EYE_CTRL_SIGNAL1 … /* RX Gen1 LEQ tuning step */ #define RG_EQ_DLEQ_LFI_GEN1_MSK … #define ANA_EQ_EYE_CTRL_SIGNAL4 … #define RG_CDR_BIRLTD0_GEN1_MSK … #define ANA_EQ_EYE_CTRL_SIGNAL5 … #define RG_CDR_BIRLTD0_GEN3_MSK … /* PHY switch between pcie/usb3/sgmii/sata */ #define USB_PHY_SWITCH_CTRL … #define RG_PHY_SW_TYPE … #define RG_PHY_SW_PCIE … #define RG_PHY_SW_USB3 … #define RG_PHY_SW_SGMII … #define RG_PHY_SW_SATA … #define TPHY_CLKS_CNT … #define USER_BUF_LEN(count) … enum mtk_phy_version { … }; struct mtk_phy_pdata { … }; struct u2phy_banks { … }; struct u3phy_banks { … }; struct mtk_phy_instance { … }; struct mtk_tphy { … }; #if IS_ENABLED(CONFIG_DEBUG_FS) enum u2_phy_params { … }; enum u3_phy_params { … }; static const char *const u2_phy_files[] = …; static const char *const u3_phy_files[] = …; static int u2_phy_params_show(struct seq_file *sf, void *unused) { … } static int u2_phy_params_open(struct inode *inode, struct file *file) { … } static ssize_t u2_phy_params_write(struct file *file, const char __user *ubuf, size_t count, loff_t *ppos) { … } static const struct file_operations u2_phy_fops = …; static void u2_phy_dbgfs_files_create(struct mtk_phy_instance *inst) { … } static int u3_phy_params_show(struct seq_file *sf, void *unused) { … } static int u3_phy_params_open(struct inode *inode, struct file *file) { … } static ssize_t u3_phy_params_write(struct file *file, const char __user *ubuf, size_t count, loff_t *ppos) { … } static const struct file_operations u3_phy_fops = …; static void u3_phy_dbgfs_files_create(struct mtk_phy_instance *inst) { … } static int phy_type_show(struct seq_file *sf, void *unused) { … } DEFINE_SHOW_ATTRIBUTE(…); /* these files will be removed when phy is released by phy core */ static void phy_debugfs_init(struct mtk_phy_instance *inst) { … } #else static void phy_debugfs_init(struct mtk_phy_instance *inst) {} #endif static void hs_slew_rate_calibrate(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) { … } static void u3_phy_instance_init(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) { … } static void u2_phy_pll_26m_set(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) { … } static void u2_phy_instance_init(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) { … } static void u2_phy_instance_power_on(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) { … } static void u2_phy_instance_power_off(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) { … } static void u2_phy_instance_exit(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) { … } static void u2_phy_instance_set_mode(struct mtk_tphy *tphy, struct mtk_phy_instance *instance, enum phy_mode mode) { … } static void pcie_phy_instance_init(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) { … } static void pcie_phy_instance_power_on(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) { … } static void pcie_phy_instance_power_off(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) { … } static void sata_phy_instance_init(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) { … } static void phy_v1_banks_init(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) { … } static void phy_v2_banks_init(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) { … } static void phy_parse_property(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) { … } static void u2_phy_props_set(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) { … } /* type switch for usb3/pcie/sgmii/sata */ static int phy_type_syscon_get(struct mtk_phy_instance *instance, struct device_node *dn) { … } static int phy_type_set(struct mtk_phy_instance *instance) { … } static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) { … } static void phy_efuse_set(struct mtk_phy_instance *instance) { … } static int mtk_phy_init(struct phy *phy) { … } static int mtk_phy_power_on(struct phy *phy) { … } static int mtk_phy_power_off(struct phy *phy) { … } static int mtk_phy_exit(struct phy *phy) { … } static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) { … } static struct phy *mtk_phy_xlate(struct device *dev, const struct of_phandle_args *args) { … } static const struct phy_ops mtk_tphy_ops = …; static const struct mtk_phy_pdata tphy_v1_pdata = …; static const struct mtk_phy_pdata tphy_v2_pdata = …; static const struct mtk_phy_pdata tphy_v3_pdata = …; static const struct mtk_phy_pdata mt8173_pdata = …; static const struct mtk_phy_pdata mt8195_pdata = …; static const struct of_device_id mtk_tphy_id_table[] = …; MODULE_DEVICE_TABLE(of, mtk_tphy_id_table); static int mtk_tphy_probe(struct platform_device *pdev) { … } static struct platform_driver mtk_tphy_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
Codebase Browser
linux