linux/include/soc/mscc/ocelot_hsio.h

/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
 * Microsemi Ocelot Switch driver
 *
 * Copyright (c) 2017 Microsemi Corporation
 */

#ifndef _MSCC_OCELOT_HSIO_H_
#define _MSCC_OCELOT_HSIO_H_

#define HSIO_PLL5G_CFG0
#define HSIO_PLL5G_CFG1
#define HSIO_PLL5G_CFG2
#define HSIO_PLL5G_CFG3
#define HSIO_PLL5G_CFG4
#define HSIO_PLL5G_CFG5
#define HSIO_PLL5G_CFG6
#define HSIO_PLL5G_STATUS0
#define HSIO_PLL5G_STATUS1
#define HSIO_PLL5G_BIST_CFG0
#define HSIO_PLL5G_BIST_CFG1
#define HSIO_PLL5G_BIST_CFG2
#define HSIO_PLL5G_BIST_STAT0
#define HSIO_PLL5G_BIST_STAT1
#define HSIO_RCOMP_CFG0
#define HSIO_RCOMP_STATUS
#define HSIO_SYNC_ETH_CFG
#define HSIO_SYNC_ETH_PLL_CFG
#define HSIO_S1G_DES_CFG
#define HSIO_S1G_IB_CFG
#define HSIO_S1G_OB_CFG
#define HSIO_S1G_SER_CFG
#define HSIO_S1G_COMMON_CFG
#define HSIO_S1G_PLL_CFG
#define HSIO_S1G_PLL_STATUS
#define HSIO_S1G_DFT_CFG0
#define HSIO_S1G_DFT_CFG1
#define HSIO_S1G_DFT_CFG2
#define HSIO_S1G_TP_CFG
#define HSIO_S1G_RC_PLL_BIST_CFG
#define HSIO_S1G_MISC_CFG
#define HSIO_S1G_DFT_STATUS
#define HSIO_S1G_MISC_STATUS
#define HSIO_MCB_S1G_ADDR_CFG
#define HSIO_S6G_DIG_CFG
#define HSIO_S6G_DFT_CFG0
#define HSIO_S6G_DFT_CFG1
#define HSIO_S6G_DFT_CFG2
#define HSIO_S6G_TP_CFG0
#define HSIO_S6G_TP_CFG1
#define HSIO_S6G_RC_PLL_BIST_CFG
#define HSIO_S6G_MISC_CFG
#define HSIO_S6G_OB_ANEG_CFG
#define HSIO_S6G_DFT_STATUS
#define HSIO_S6G_ERR_CNT
#define HSIO_S6G_MISC_STATUS
#define HSIO_S6G_DES_CFG
#define HSIO_S6G_IB_CFG
#define HSIO_S6G_IB_CFG1
#define HSIO_S6G_IB_CFG2
#define HSIO_S6G_IB_CFG3
#define HSIO_S6G_IB_CFG4
#define HSIO_S6G_IB_CFG5
#define HSIO_S6G_OB_CFG
#define HSIO_S6G_OB_CFG1
#define HSIO_S6G_SER_CFG
#define HSIO_S6G_COMMON_CFG
#define HSIO_S6G_PLL_CFG
#define HSIO_S6G_ACJTAG_CFG
#define HSIO_S6G_GP_CFG
#define HSIO_S6G_IB_STATUS0
#define HSIO_S6G_IB_STATUS1
#define HSIO_S6G_ACJTAG_STATUS
#define HSIO_S6G_PLL_STATUS
#define HSIO_S6G_REVID
#define HSIO_MCB_S6G_ADDR_CFG
#define HSIO_HW_CFG
#define HSIO_HW_QSGMII_CFG
#define HSIO_HW_QSGMII_STAT
#define HSIO_CLK_CFG
#define HSIO_TEMP_SENSOR_CTRL
#define HSIO_TEMP_SENSOR_CFG
#define HSIO_TEMP_SENSOR_STAT

#define HSIO_PLL5G_CFG0_ENA_ROT
#define HSIO_PLL5G_CFG0_ENA_LANE
#define HSIO_PLL5G_CFG0_ENA_CLKTREE
#define HSIO_PLL5G_CFG0_DIV4
#define HSIO_PLL5G_CFG0_ENA_LOCK_FINE
#define HSIO_PLL5G_CFG0_SELBGV820(x)
#define HSIO_PLL5G_CFG0_SELBGV820_M
#define HSIO_PLL5G_CFG0_SELBGV820_X(x)
#define HSIO_PLL5G_CFG0_LOOP_BW_RES(x)
#define HSIO_PLL5G_CFG0_LOOP_BW_RES_M
#define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x)
#define HSIO_PLL5G_CFG0_SELCPI(x)
#define HSIO_PLL5G_CFG0_SELCPI_M
#define HSIO_PLL5G_CFG0_SELCPI_X(x)
#define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH
#define HSIO_PLL5G_CFG0_ENA_CP1
#define HSIO_PLL5G_CFG0_ENA_VCO_BUF
#define HSIO_PLL5G_CFG0_ENA_BIAS
#define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x)
#define HSIO_PLL5G_CFG0_CPU_CLK_DIV_M
#define HSIO_PLL5G_CFG0_CPU_CLK_DIV_X(x)
#define HSIO_PLL5G_CFG0_CORE_CLK_DIV(x)
#define HSIO_PLL5G_CFG0_CORE_CLK_DIV_M

#define HSIO_PLL5G_CFG1_ENA_DIRECT
#define HSIO_PLL5G_CFG1_ROT_SPEED
#define HSIO_PLL5G_CFG1_ROT_DIR
#define HSIO_PLL5G_CFG1_READBACK_DATA_SEL
#define HSIO_PLL5G_CFG1_RC_ENABLE
#define HSIO_PLL5G_CFG1_RC_CTRL_DATA(x)
#define HSIO_PLL5G_CFG1_RC_CTRL_DATA_M
#define HSIO_PLL5G_CFG1_RC_CTRL_DATA_X(x)
#define HSIO_PLL5G_CFG1_QUARTER_RATE
#define HSIO_PLL5G_CFG1_PWD_TX
#define HSIO_PLL5G_CFG1_PWD_RX
#define HSIO_PLL5G_CFG1_OUT_OF_RANGE_RECAL_ENA
#define HSIO_PLL5G_CFG1_HALF_RATE
#define HSIO_PLL5G_CFG1_FORCE_SET_ENA

#define HSIO_PLL5G_CFG2_ENA_TEST_MODE
#define HSIO_PLL5G_CFG2_ENA_PFD_IN_FLIP
#define HSIO_PLL5G_CFG2_ENA_VCO_NREF_TESTOUT
#define HSIO_PLL5G_CFG2_ENA_FBTESTOUT
#define HSIO_PLL5G_CFG2_ENA_RCPLL
#define HSIO_PLL5G_CFG2_ENA_CP2
#define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS1
#define HSIO_PLL5G_CFG2_AMPC_SEL(x)
#define HSIO_PLL5G_CFG2_AMPC_SEL_M
#define HSIO_PLL5G_CFG2_AMPC_SEL_X(x)
#define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS
#define HSIO_PLL5G_CFG2_PWD_AMPCTRL_N
#define HSIO_PLL5G_CFG2_ENA_AMPCTRL
#define HSIO_PLL5G_CFG2_ENA_AMP_CTRL_FORCE
#define HSIO_PLL5G_CFG2_FRC_FSM_POR
#define HSIO_PLL5G_CFG2_DISABLE_FSM_POR
#define HSIO_PLL5G_CFG2_GAIN_TEST(x)
#define HSIO_PLL5G_CFG2_GAIN_TEST_M
#define HSIO_PLL5G_CFG2_GAIN_TEST_X(x)
#define HSIO_PLL5G_CFG2_EN_RESET_OVERRUN
#define HSIO_PLL5G_CFG2_EN_RESET_LIM_DET
#define HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET
#define HSIO_PLL5G_CFG2_DISABLE_FSM
#define HSIO_PLL5G_CFG2_ENA_GAIN_TEST

#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL(x)
#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_M
#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_X(x)
#define HSIO_PLL5G_CFG3_TESTOUT_SEL(x)
#define HSIO_PLL5G_CFG3_TESTOUT_SEL_M
#define HSIO_PLL5G_CFG3_TESTOUT_SEL_X(x)
#define HSIO_PLL5G_CFG3_ENA_ANA_TEST_OUT
#define HSIO_PLL5G_CFG3_ENA_TEST_OUT
#define HSIO_PLL5G_CFG3_SEL_FBDCLK
#define HSIO_PLL5G_CFG3_SEL_CML_CMOS_PFD
#define HSIO_PLL5G_CFG3_RST_FB_N
#define HSIO_PLL5G_CFG3_FORCE_VCO_CONTRH
#define HSIO_PLL5G_CFG3_FORCE_LO
#define HSIO_PLL5G_CFG3_FORCE_HI
#define HSIO_PLL5G_CFG3_FORCE_ENA
#define HSIO_PLL5G_CFG3_FORCE_CP
#define HSIO_PLL5G_CFG3_FBDIVSEL_TST_ENA
#define HSIO_PLL5G_CFG3_FBDIVSEL(x)
#define HSIO_PLL5G_CFG3_FBDIVSEL_M

#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL(x)
#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_M
#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_X(x)
#define HSIO_PLL5G_CFG4_IB_CTRL(x)
#define HSIO_PLL5G_CFG4_IB_CTRL_M

#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL(x)
#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_M
#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_X(x)
#define HSIO_PLL5G_CFG5_OB_CTRL(x)
#define HSIO_PLL5G_CFG5_OB_CTRL_M

#define HSIO_PLL5G_CFG6_REFCLK_SEL_SRC
#define HSIO_PLL5G_CFG6_REFCLK_SEL(x)
#define HSIO_PLL5G_CFG6_REFCLK_SEL_M
#define HSIO_PLL5G_CFG6_REFCLK_SEL_X(x)
#define HSIO_PLL5G_CFG6_REFCLK_SRC
#define HSIO_PLL5G_CFG6_POR_DEL_SEL(x)
#define HSIO_PLL5G_CFG6_POR_DEL_SEL_M
#define HSIO_PLL5G_CFG6_POR_DEL_SEL_X(x)
#define HSIO_PLL5G_CFG6_DIV125REF_SEL(x)
#define HSIO_PLL5G_CFG6_DIV125REF_SEL_M
#define HSIO_PLL5G_CFG6_DIV125REF_SEL_X(x)
#define HSIO_PLL5G_CFG6_ENA_REFCLKC2
#define HSIO_PLL5G_CFG6_ENA_FBCLKC2
#define HSIO_PLL5G_CFG6_DDR_CLK_DIV(x)
#define HSIO_PLL5G_CFG6_DDR_CLK_DIV_M

#define HSIO_PLL5G_STATUS0_RANGE_LIM
#define HSIO_PLL5G_STATUS0_OUT_OF_RANGE_ERR
#define HSIO_PLL5G_STATUS0_CALIBRATION_ERR
#define HSIO_PLL5G_STATUS0_CALIBRATION_DONE
#define HSIO_PLL5G_STATUS0_READBACK_DATA(x)
#define HSIO_PLL5G_STATUS0_READBACK_DATA_M
#define HSIO_PLL5G_STATUS0_READBACK_DATA_X(x)
#define HSIO_PLL5G_STATUS0_LOCK_STATUS

#define HSIO_PLL5G_STATUS1_SIG_DEL(x)
#define HSIO_PLL5G_STATUS1_SIG_DEL_M
#define HSIO_PLL5G_STATUS1_SIG_DEL_X(x)
#define HSIO_PLL5G_STATUS1_GAIN_STAT(x)
#define HSIO_PLL5G_STATUS1_GAIN_STAT_M
#define HSIO_PLL5G_STATUS1_GAIN_STAT_X(x)
#define HSIO_PLL5G_STATUS1_FBCNT_DIF(x)
#define HSIO_PLL5G_STATUS1_FBCNT_DIF_M
#define HSIO_PLL5G_STATUS1_FBCNT_DIF_X(x)
#define HSIO_PLL5G_STATUS1_FSM_STAT(x)
#define HSIO_PLL5G_STATUS1_FSM_STAT_M
#define HSIO_PLL5G_STATUS1_FSM_STAT_X(x)
#define HSIO_PLL5G_STATUS1_FSM_LOCK

#define HSIO_PLL5G_BIST_CFG0_PLLB_START_BIST
#define HSIO_PLL5G_BIST_CFG0_PLLB_MEAS_MODE
#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT(x)
#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_M
#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_X(x)
#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT(x)
#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_M
#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_X(x)
#define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE(x)
#define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE_M

#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT(x)
#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_M
#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_X(x)
#define HSIO_PLL5G_BIST_STAT0_PLLB_BUSY
#define HSIO_PLL5G_BIST_STAT0_PLLB_DONE_N
#define HSIO_PLL5G_BIST_STAT0_PLLB_FAIL

#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT(x)
#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_M
#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_X(x)
#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF(x)
#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF_M

#define HSIO_RCOMP_CFG0_PWD_ENA
#define HSIO_RCOMP_CFG0_RUN_CAL
#define HSIO_RCOMP_CFG0_SPEED_SEL(x)
#define HSIO_RCOMP_CFG0_SPEED_SEL_M
#define HSIO_RCOMP_CFG0_SPEED_SEL_X(x)
#define HSIO_RCOMP_CFG0_MODE_SEL(x)
#define HSIO_RCOMP_CFG0_MODE_SEL_M
#define HSIO_RCOMP_CFG0_MODE_SEL_X(x)
#define HSIO_RCOMP_CFG0_FORCE_ENA
#define HSIO_RCOMP_CFG0_RCOMP_VAL(x)
#define HSIO_RCOMP_CFG0_RCOMP_VAL_M

#define HSIO_RCOMP_STATUS_BUSY
#define HSIO_RCOMP_STATUS_DELTA_ALERT
#define HSIO_RCOMP_STATUS_RCOMP(x)
#define HSIO_RCOMP_STATUS_RCOMP_M

#define HSIO_SYNC_ETH_CFG_RSZ

#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC(x)
#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_M
#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_X(x)
#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV(x)
#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_M
#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_X(x)
#define HSIO_SYNC_ETH_CFG_RECO_CLK_ENA

#define HSIO_SYNC_ETH_PLL_CFG_PLL_AUTO_SQUELCH_ENA

#define HSIO_S1G_DES_CFG_DES_PHS_CTRL(x)
#define HSIO_S1G_DES_CFG_DES_PHS_CTRL_M
#define HSIO_S1G_DES_CFG_DES_PHS_CTRL_X(x)
#define HSIO_S1G_DES_CFG_DES_CPMD_SEL(x)
#define HSIO_S1G_DES_CFG_DES_CPMD_SEL_M
#define HSIO_S1G_DES_CFG_DES_CPMD_SEL_X(x)
#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL(x)
#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_M
#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_X(x)
#define HSIO_S1G_DES_CFG_DES_BW_ANA(x)
#define HSIO_S1G_DES_CFG_DES_BW_ANA_M
#define HSIO_S1G_DES_CFG_DES_BW_ANA_X(x)
#define HSIO_S1G_DES_CFG_DES_SWAP_ANA
#define HSIO_S1G_DES_CFG_DES_BW_HYST(x)
#define HSIO_S1G_DES_CFG_DES_BW_HYST_M
#define HSIO_S1G_DES_CFG_DES_BW_HYST_X(x)
#define HSIO_S1G_DES_CFG_DES_SWAP_HYST

#define HSIO_S1G_IB_CFG_IB_FX100_ENA
#define HSIO_S1G_IB_CFG_ACJTAG_HYST(x)
#define HSIO_S1G_IB_CFG_ACJTAG_HYST_M
#define HSIO_S1G_IB_CFG_ACJTAG_HYST_X(x)
#define HSIO_S1G_IB_CFG_IB_DET_LEV(x)
#define HSIO_S1G_IB_CFG_IB_DET_LEV_M
#define HSIO_S1G_IB_CFG_IB_DET_LEV_X(x)
#define HSIO_S1G_IB_CFG_IB_HYST_LEV
#define HSIO_S1G_IB_CFG_IB_ENA_CMV_TERM
#define HSIO_S1G_IB_CFG_IB_ENA_DC_COUPLING
#define HSIO_S1G_IB_CFG_IB_ENA_DETLEV
#define HSIO_S1G_IB_CFG_IB_ENA_HYST
#define HSIO_S1G_IB_CFG_IB_ENA_OFFSET_COMP
#define HSIO_S1G_IB_CFG_IB_EQ_GAIN(x)
#define HSIO_S1G_IB_CFG_IB_EQ_GAIN_M
#define HSIO_S1G_IB_CFG_IB_EQ_GAIN_X(x)
#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ(x)
#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_M
#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_X(x)
#define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL(x)
#define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL_M

#define HSIO_S1G_OB_CFG_OB_SLP(x)
#define HSIO_S1G_OB_CFG_OB_SLP_M
#define HSIO_S1G_OB_CFG_OB_SLP_X(x)
#define HSIO_S1G_OB_CFG_OB_AMP_CTRL(x)
#define HSIO_S1G_OB_CFG_OB_AMP_CTRL_M
#define HSIO_S1G_OB_CFG_OB_AMP_CTRL_X(x)
#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL(x)
#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_M
#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_X(x)
#define HSIO_S1G_OB_CFG_OB_DIS_VCM_CTRL
#define HSIO_S1G_OB_CFG_OB_EN_MEAS_VREG
#define HSIO_S1G_OB_CFG_OB_VCM_CTRL(x)
#define HSIO_S1G_OB_CFG_OB_VCM_CTRL_M
#define HSIO_S1G_OB_CFG_OB_VCM_CTRL_X(x)
#define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL(x)
#define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL_M

#define HSIO_S1G_SER_CFG_SER_IDLE
#define HSIO_S1G_SER_CFG_SER_DEEMPH
#define HSIO_S1G_SER_CFG_SER_CPMD_SEL
#define HSIO_S1G_SER_CFG_SER_SWAP_CPMD
#define HSIO_S1G_SER_CFG_SER_ALISEL(x)
#define HSIO_S1G_SER_CFG_SER_ALISEL_M
#define HSIO_S1G_SER_CFG_SER_ALISEL_X(x)
#define HSIO_S1G_SER_CFG_SER_ENHYS
#define HSIO_S1G_SER_CFG_SER_BIG_WIN
#define HSIO_S1G_SER_CFG_SER_EN_WIN
#define HSIO_S1G_SER_CFG_SER_ENALI

#define HSIO_S1G_COMMON_CFG_SYS_RST
#define HSIO_S1G_COMMON_CFG_SE_AUTO_SQUELCH_ENA
#define HSIO_S1G_COMMON_CFG_ENA_LANE
#define HSIO_S1G_COMMON_CFG_PWD_RX
#define HSIO_S1G_COMMON_CFG_PWD_TX
#define HSIO_S1G_COMMON_CFG_LANE_CTRL(x)
#define HSIO_S1G_COMMON_CFG_LANE_CTRL_M
#define HSIO_S1G_COMMON_CFG_LANE_CTRL_X(x)
#define HSIO_S1G_COMMON_CFG_ENA_DIRECT
#define HSIO_S1G_COMMON_CFG_ENA_ELOOP
#define HSIO_S1G_COMMON_CFG_ENA_FLOOP
#define HSIO_S1G_COMMON_CFG_ENA_ILOOP
#define HSIO_S1G_COMMON_CFG_ENA_PLOOP
#define HSIO_S1G_COMMON_CFG_HRATE
#define HSIO_S1G_COMMON_CFG_IF_MODE

#define HSIO_S1G_PLL_CFG_PLL_ENA_FB_DIV2
#define HSIO_S1G_PLL_CFG_PLL_ENA_RC_DIV2
#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA(x)
#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_M
#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x)
#define HSIO_S1G_PLL_CFG_PLL_FSM_ENA
#define HSIO_S1G_PLL_CFG_PLL_FSM_FORCE_SET_ENA
#define HSIO_S1G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA
#define HSIO_S1G_PLL_CFG_PLL_RB_DATA_SEL

#define HSIO_S1G_PLL_STATUS_PLL_CAL_NOT_DONE
#define HSIO_S1G_PLL_STATUS_PLL_CAL_ERR
#define HSIO_S1G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR
#define HSIO_S1G_PLL_STATUS_PLL_RB_DATA(x)
#define HSIO_S1G_PLL_STATUS_PLL_RB_DATA_M

#define HSIO_S1G_DFT_CFG0_LAZYBIT
#define HSIO_S1G_DFT_CFG0_INV_DIS
#define HSIO_S1G_DFT_CFG0_PRBS_SEL(x)
#define HSIO_S1G_DFT_CFG0_PRBS_SEL_M
#define HSIO_S1G_DFT_CFG0_PRBS_SEL_X(x)
#define HSIO_S1G_DFT_CFG0_TEST_MODE(x)
#define HSIO_S1G_DFT_CFG0_TEST_MODE_M
#define HSIO_S1G_DFT_CFG0_TEST_MODE_X(x)
#define HSIO_S1G_DFT_CFG0_RX_PHS_CORR_DIS
#define HSIO_S1G_DFT_CFG0_RX_PDSENS_ENA
#define HSIO_S1G_DFT_CFG0_RX_DFT_ENA
#define HSIO_S1G_DFT_CFG0_TX_DFT_ENA

#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL(x)
#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_M
#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_X(x)
#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ(x)
#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_M
#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_X(x)
#define HSIO_S1G_DFT_CFG1_TX_JI_ENA
#define HSIO_S1G_DFT_CFG1_TX_WAVEFORM_SEL
#define HSIO_S1G_DFT_CFG1_TX_FREQOFF_DIR
#define HSIO_S1G_DFT_CFG1_TX_FREQOFF_ENA

#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL(x)
#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_M
#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_X(x)
#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ(x)
#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_M
#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_X(x)
#define HSIO_S1G_DFT_CFG2_RX_JI_ENA
#define HSIO_S1G_DFT_CFG2_RX_WAVEFORM_SEL
#define HSIO_S1G_DFT_CFG2_RX_FREQOFF_DIR
#define HSIO_S1G_DFT_CFG2_RX_FREQOFF_ENA

#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_ENA
#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x)
#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M
#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x)
#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x)
#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M
#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x)
#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x)
#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M

#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE(x)
#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_M
#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_X(x)
#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_SWAP
#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_MODE
#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_ENA
#define HSIO_S1G_MISC_CFG_RX_LPI_MODE_ENA
#define HSIO_S1G_MISC_CFG_TX_LPI_MODE_ENA
#define HSIO_S1G_MISC_CFG_RX_DATA_INV_ENA
#define HSIO_S1G_MISC_CFG_TX_DATA_INV_ENA
#define HSIO_S1G_MISC_CFG_LANE_RST

#define HSIO_S1G_DFT_STATUS_PLL_BIST_NOT_DONE
#define HSIO_S1G_DFT_STATUS_PLL_BIST_FAILED
#define HSIO_S1G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR
#define HSIO_S1G_DFT_STATUS_BIST_ACTIVE
#define HSIO_S1G_DFT_STATUS_BIST_NOSYNC
#define HSIO_S1G_DFT_STATUS_BIST_COMPLETE_N
#define HSIO_S1G_DFT_STATUS_BIST_ERROR

#define HSIO_S1G_MISC_STATUS_DES_100FX_PHASE_SEL

#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_WR_ONE_SHOT
#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_RD_ONE_SHOT
#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR(x)
#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR_M

#define HSIO_S6G_DIG_CFG_GP(x)
#define HSIO_S6G_DIG_CFG_GP_M
#define HSIO_S6G_DIG_CFG_GP_X(x)
#define HSIO_S6G_DIG_CFG_TX_BIT_DOUBLING_MODE_ENA
#define HSIO_S6G_DIG_CFG_SIGDET_TESTMODE
#define HSIO_S6G_DIG_CFG_SIGDET_AST(x)
#define HSIO_S6G_DIG_CFG_SIGDET_AST_M
#define HSIO_S6G_DIG_CFG_SIGDET_AST_X(x)
#define HSIO_S6G_DIG_CFG_SIGDET_DST(x)
#define HSIO_S6G_DIG_CFG_SIGDET_DST_M

#define HSIO_S6G_DFT_CFG0_LAZYBIT
#define HSIO_S6G_DFT_CFG0_INV_DIS
#define HSIO_S6G_DFT_CFG0_PRBS_SEL(x)
#define HSIO_S6G_DFT_CFG0_PRBS_SEL_M
#define HSIO_S6G_DFT_CFG0_PRBS_SEL_X(x)
#define HSIO_S6G_DFT_CFG0_TEST_MODE(x)
#define HSIO_S6G_DFT_CFG0_TEST_MODE_M
#define HSIO_S6G_DFT_CFG0_TEST_MODE_X(x)
#define HSIO_S6G_DFT_CFG0_RX_PHS_CORR_DIS
#define HSIO_S6G_DFT_CFG0_RX_PDSENS_ENA
#define HSIO_S6G_DFT_CFG0_RX_DFT_ENA
#define HSIO_S6G_DFT_CFG0_TX_DFT_ENA

#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL(x)
#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_M
#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_X(x)
#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ(x)
#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_M
#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_X(x)
#define HSIO_S6G_DFT_CFG1_TX_JI_ENA
#define HSIO_S6G_DFT_CFG1_TX_WAVEFORM_SEL
#define HSIO_S6G_DFT_CFG1_TX_FREQOFF_DIR
#define HSIO_S6G_DFT_CFG1_TX_FREQOFF_ENA

#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL(x)
#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_M
#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_X(x)
#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ(x)
#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_M
#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_X(x)
#define HSIO_S6G_DFT_CFG2_RX_JI_ENA
#define HSIO_S6G_DFT_CFG2_RX_WAVEFORM_SEL
#define HSIO_S6G_DFT_CFG2_RX_FREQOFF_DIR
#define HSIO_S6G_DFT_CFG2_RX_FREQOFF_ENA

#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_ENA
#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x)
#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M
#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x)
#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x)
#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M
#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x)
#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x)
#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M

#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK(x)
#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_M
#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_X(x)
#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE(x)
#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_M
#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_X(x)
#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_SWAP
#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_MODE
#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_ENA
#define HSIO_S6G_MISC_CFG_RX_BUS_FLIP_ENA
#define HSIO_S6G_MISC_CFG_TX_BUS_FLIP_ENA
#define HSIO_S6G_MISC_CFG_RX_LPI_MODE_ENA
#define HSIO_S6G_MISC_CFG_TX_LPI_MODE_ENA
#define HSIO_S6G_MISC_CFG_RX_DATA_INV_ENA
#define HSIO_S6G_MISC_CFG_TX_DATA_INV_ENA
#define HSIO_S6G_MISC_CFG_LANE_RST

#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0(x)
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_M
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_X(x)
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1(x)
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_M
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_X(x)
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC(x)
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_M
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_X(x)
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS(x)
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_M
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_X(x)
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV(x)
#define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV_M

#define HSIO_S6G_DFT_STATUS_PRBS_SYNC_STAT
#define HSIO_S6G_DFT_STATUS_PLL_BIST_NOT_DONE
#define HSIO_S6G_DFT_STATUS_PLL_BIST_FAILED
#define HSIO_S6G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR
#define HSIO_S6G_DFT_STATUS_BIST_ACTIVE
#define HSIO_S6G_DFT_STATUS_BIST_NOSYNC
#define HSIO_S6G_DFT_STATUS_BIST_COMPLETE_N
#define HSIO_S6G_DFT_STATUS_BIST_ERROR

#define HSIO_S6G_MISC_STATUS_DES_100FX_PHASE_SEL

#define HSIO_S6G_DES_CFG_DES_PHS_CTRL(x)
#define HSIO_S6G_DES_CFG_DES_PHS_CTRL_M
#define HSIO_S6G_DES_CFG_DES_PHS_CTRL_X(x)
#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL(x)
#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_M
#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_X(x)
#define HSIO_S6G_DES_CFG_DES_CPMD_SEL(x)
#define HSIO_S6G_DES_CFG_DES_CPMD_SEL_M
#define HSIO_S6G_DES_CFG_DES_CPMD_SEL_X(x)
#define HSIO_S6G_DES_CFG_DES_BW_HYST(x)
#define HSIO_S6G_DES_CFG_DES_BW_HYST_M
#define HSIO_S6G_DES_CFG_DES_BW_HYST_X(x)
#define HSIO_S6G_DES_CFG_DES_SWAP_HYST
#define HSIO_S6G_DES_CFG_DES_BW_ANA(x)
#define HSIO_S6G_DES_CFG_DES_BW_ANA_M
#define HSIO_S6G_DES_CFG_DES_BW_ANA_X(x)
#define HSIO_S6G_DES_CFG_DES_SWAP_ANA

#define HSIO_S6G_IB_CFG_IB_SOFSI(x)
#define HSIO_S6G_IB_CFG_IB_SOFSI_M
#define HSIO_S6G_IB_CFG_IB_SOFSI_X(x)
#define HSIO_S6G_IB_CFG_IB_VBULK_SEL
#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ(x)
#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_M
#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_X(x)
#define HSIO_S6G_IB_CFG_IB_ICML_ADJ(x)
#define HSIO_S6G_IB_CFG_IB_ICML_ADJ_M
#define HSIO_S6G_IB_CFG_IB_ICML_ADJ_X(x)
#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL(x)
#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_M
#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_X(x)
#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL(x)
#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_M
#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_X(x)
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP(x)
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_M
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_X(x)
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID(x)
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_M
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_X(x)
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP(x)
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_M
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_X(x)
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET(x)
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_M
#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_X(x)
#define HSIO_S6G_IB_CFG_IB_ANA_TEST_ENA
#define HSIO_S6G_IB_CFG_IB_SIG_DET_ENA
#define HSIO_S6G_IB_CFG_IB_CONCUR
#define HSIO_S6G_IB_CFG_IB_CAL_ENA
#define HSIO_S6G_IB_CFG_IB_SAM_ENA
#define HSIO_S6G_IB_CFG_IB_EQZ_ENA
#define HSIO_S6G_IB_CFG_IB_REG_ENA

#define HSIO_S6G_IB_CFG1_IB_TJTAG(x)
#define HSIO_S6G_IB_CFG1_IB_TJTAG_M
#define HSIO_S6G_IB_CFG1_IB_TJTAG_X(x)
#define HSIO_S6G_IB_CFG1_IB_TSDET(x)
#define HSIO_S6G_IB_CFG1_IB_TSDET_M
#define HSIO_S6G_IB_CFG1_IB_TSDET_X(x)
#define HSIO_S6G_IB_CFG1_IB_SCALY(x)
#define HSIO_S6G_IB_CFG1_IB_SCALY_M
#define HSIO_S6G_IB_CFG1_IB_SCALY_X(x)
#define HSIO_S6G_IB_CFG1_IB_FILT_HP
#define HSIO_S6G_IB_CFG1_IB_FILT_MID
#define HSIO_S6G_IB_CFG1_IB_FILT_LP
#define HSIO_S6G_IB_CFG1_IB_FILT_OFFSET
#define HSIO_S6G_IB_CFG1_IB_FRC_HP
#define HSIO_S6G_IB_CFG1_IB_FRC_MID
#define HSIO_S6G_IB_CFG1_IB_FRC_LP
#define HSIO_S6G_IB_CFG1_IB_FRC_OFFSET

#define HSIO_S6G_IB_CFG2_IB_TINFV(x)
#define HSIO_S6G_IB_CFG2_IB_TINFV_M
#define HSIO_S6G_IB_CFG2_IB_TINFV_X(x)
#define HSIO_S6G_IB_CFG2_IB_OINFI(x)
#define HSIO_S6G_IB_CFG2_IB_OINFI_M
#define HSIO_S6G_IB_CFG2_IB_OINFI_X(x)
#define HSIO_S6G_IB_CFG2_IB_TAUX(x)
#define HSIO_S6G_IB_CFG2_IB_TAUX_M
#define HSIO_S6G_IB_CFG2_IB_TAUX_X(x)
#define HSIO_S6G_IB_CFG2_IB_OINFS(x)
#define HSIO_S6G_IB_CFG2_IB_OINFS_M
#define HSIO_S6G_IB_CFG2_IB_OINFS_X(x)
#define HSIO_S6G_IB_CFG2_IB_OCALS(x)
#define HSIO_S6G_IB_CFG2_IB_OCALS_M
#define HSIO_S6G_IB_CFG2_IB_OCALS_X(x)
#define HSIO_S6G_IB_CFG2_IB_TCALV(x)
#define HSIO_S6G_IB_CFG2_IB_TCALV_M
#define HSIO_S6G_IB_CFG2_IB_TCALV_X(x)
#define HSIO_S6G_IB_CFG2_IB_UMAX(x)
#define HSIO_S6G_IB_CFG2_IB_UMAX_M
#define HSIO_S6G_IB_CFG2_IB_UMAX_X(x)
#define HSIO_S6G_IB_CFG2_IB_UREG(x)
#define HSIO_S6G_IB_CFG2_IB_UREG_M

#define HSIO_S6G_IB_CFG3_IB_INI_HP(x)
#define HSIO_S6G_IB_CFG3_IB_INI_HP_M
#define HSIO_S6G_IB_CFG3_IB_INI_HP_X(x)
#define HSIO_S6G_IB_CFG3_IB_INI_MID(x)
#define HSIO_S6G_IB_CFG3_IB_INI_MID_M
#define HSIO_S6G_IB_CFG3_IB_INI_MID_X(x)
#define HSIO_S6G_IB_CFG3_IB_INI_LP(x)
#define HSIO_S6G_IB_CFG3_IB_INI_LP_M
#define HSIO_S6G_IB_CFG3_IB_INI_LP_X(x)
#define HSIO_S6G_IB_CFG3_IB_INI_OFFSET(x)
#define HSIO_S6G_IB_CFG3_IB_INI_OFFSET_M

#define HSIO_S6G_IB_CFG4_IB_MAX_HP(x)
#define HSIO_S6G_IB_CFG4_IB_MAX_HP_M
#define HSIO_S6G_IB_CFG4_IB_MAX_HP_X(x)
#define HSIO_S6G_IB_CFG4_IB_MAX_MID(x)
#define HSIO_S6G_IB_CFG4_IB_MAX_MID_M
#define HSIO_S6G_IB_CFG4_IB_MAX_MID_X(x)
#define HSIO_S6G_IB_CFG4_IB_MAX_LP(x)
#define HSIO_S6G_IB_CFG4_IB_MAX_LP_M
#define HSIO_S6G_IB_CFG4_IB_MAX_LP_X(x)
#define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET(x)
#define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET_M

#define HSIO_S6G_IB_CFG5_IB_MIN_HP(x)
#define HSIO_S6G_IB_CFG5_IB_MIN_HP_M
#define HSIO_S6G_IB_CFG5_IB_MIN_HP_X(x)
#define HSIO_S6G_IB_CFG5_IB_MIN_MID(x)
#define HSIO_S6G_IB_CFG5_IB_MIN_MID_M
#define HSIO_S6G_IB_CFG5_IB_MIN_MID_X(x)
#define HSIO_S6G_IB_CFG5_IB_MIN_LP(x)
#define HSIO_S6G_IB_CFG5_IB_MIN_LP_M
#define HSIO_S6G_IB_CFG5_IB_MIN_LP_X(x)
#define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET(x)
#define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET_M

#define HSIO_S6G_OB_CFG_OB_IDLE
#define HSIO_S6G_OB_CFG_OB_ENA1V_MODE
#define HSIO_S6G_OB_CFG_OB_POL
#define HSIO_S6G_OB_CFG_OB_POST0(x)
#define HSIO_S6G_OB_CFG_OB_POST0_M
#define HSIO_S6G_OB_CFG_OB_POST0_X(x)
#define HSIO_S6G_OB_CFG_OB_PREC(x)
#define HSIO_S6G_OB_CFG_OB_PREC_M
#define HSIO_S6G_OB_CFG_OB_PREC_X(x)
#define HSIO_S6G_OB_CFG_OB_R_ADJ_MUX
#define HSIO_S6G_OB_CFG_OB_R_ADJ_PDR
#define HSIO_S6G_OB_CFG_OB_POST1(x)
#define HSIO_S6G_OB_CFG_OB_POST1_M
#define HSIO_S6G_OB_CFG_OB_POST1_X(x)
#define HSIO_S6G_OB_CFG_OB_R_COR
#define HSIO_S6G_OB_CFG_OB_SEL_RCTRL
#define HSIO_S6G_OB_CFG_OB_SR_H
#define HSIO_S6G_OB_CFG_OB_SR(x)
#define HSIO_S6G_OB_CFG_OB_SR_M
#define HSIO_S6G_OB_CFG_OB_SR_X(x)
#define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL(x)
#define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL_M

#define HSIO_S6G_OB_CFG1_OB_ENA_CAS(x)
#define HSIO_S6G_OB_CFG1_OB_ENA_CAS_M
#define HSIO_S6G_OB_CFG1_OB_ENA_CAS_X(x)
#define HSIO_S6G_OB_CFG1_OB_LEV(x)
#define HSIO_S6G_OB_CFG1_OB_LEV_M

#define HSIO_S6G_SER_CFG_SER_4TAP_ENA
#define HSIO_S6G_SER_CFG_SER_CPMD_SEL
#define HSIO_S6G_SER_CFG_SER_SWAP_CPMD
#define HSIO_S6G_SER_CFG_SER_ALISEL(x)
#define HSIO_S6G_SER_CFG_SER_ALISEL_M
#define HSIO_S6G_SER_CFG_SER_ALISEL_X(x)
#define HSIO_S6G_SER_CFG_SER_ENHYS
#define HSIO_S6G_SER_CFG_SER_BIG_WIN
#define HSIO_S6G_SER_CFG_SER_EN_WIN
#define HSIO_S6G_SER_CFG_SER_ENALI

#define HSIO_S6G_COMMON_CFG_SYS_RST
#define HSIO_S6G_COMMON_CFG_SE_DIV2_ENA
#define HSIO_S6G_COMMON_CFG_SE_AUTO_SQUELCH_ENA
#define HSIO_S6G_COMMON_CFG_ENA_LANE
#define HSIO_S6G_COMMON_CFG_PWD_RX
#define HSIO_S6G_COMMON_CFG_PWD_TX
#define HSIO_S6G_COMMON_CFG_LANE_CTRL(x)
#define HSIO_S6G_COMMON_CFG_LANE_CTRL_M
#define HSIO_S6G_COMMON_CFG_LANE_CTRL_X(x)
#define HSIO_S6G_COMMON_CFG_ENA_DIRECT
#define HSIO_S6G_COMMON_CFG_ENA_ELOOP
#define HSIO_S6G_COMMON_CFG_ENA_FLOOP
#define HSIO_S6G_COMMON_CFG_ENA_ILOOP
#define HSIO_S6G_COMMON_CFG_ENA_PLOOP
#define HSIO_S6G_COMMON_CFG_HRATE
#define HSIO_S6G_COMMON_CFG_QRATE
#define HSIO_S6G_COMMON_CFG_IF_MODE(x)
#define HSIO_S6G_COMMON_CFG_IF_MODE_M

#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS(x)
#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_M
#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_X(x)
#define HSIO_S6G_PLL_CFG_PLL_DIV4
#define HSIO_S6G_PLL_CFG_PLL_ENA_ROT
#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA(x)
#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_M
#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x)
#define HSIO_S6G_PLL_CFG_PLL_FSM_ENA
#define HSIO_S6G_PLL_CFG_PLL_FSM_FORCE_SET_ENA
#define HSIO_S6G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA
#define HSIO_S6G_PLL_CFG_PLL_RB_DATA_SEL
#define HSIO_S6G_PLL_CFG_PLL_ROT_DIR
#define HSIO_S6G_PLL_CFG_PLL_ROT_FRQ

#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_N
#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_P
#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_CLK
#define HSIO_S6G_ACJTAG_CFG_OB_DIRECT
#define HSIO_S6G_ACJTAG_CFG_ACJTAG_ENA
#define HSIO_S6G_ACJTAG_CFG_JTAG_CTRL_ENA

#define HSIO_S6G_GP_CFG_GP_MSB(x)
#define HSIO_S6G_GP_CFG_GP_MSB_M
#define HSIO_S6G_GP_CFG_GP_MSB_X(x)
#define HSIO_S6G_GP_CFG_GP_LSB(x)
#define HSIO_S6G_GP_CFG_GP_LSB_M

#define HSIO_S6G_IB_STATUS0_IB_CAL_DONE
#define HSIO_S6G_IB_STATUS0_IB_HP_GAIN_ACT
#define HSIO_S6G_IB_STATUS0_IB_MID_GAIN_ACT
#define HSIO_S6G_IB_STATUS0_IB_LP_GAIN_ACT
#define HSIO_S6G_IB_STATUS0_IB_OFFSET_ACT
#define HSIO_S6G_IB_STATUS0_IB_OFFSET_VLD
#define HSIO_S6G_IB_STATUS0_IB_OFFSET_ERR
#define HSIO_S6G_IB_STATUS0_IB_OFFSDIR
#define HSIO_S6G_IB_STATUS0_IB_SIG_DET

#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT(x)
#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_M
#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_X(x)
#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT(x)
#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_M
#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_X(x)
#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT(x)
#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_M
#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_X(x)
#define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT(x)
#define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT_M

#define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_N
#define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_P
#define HSIO_S6G_ACJTAG_STATUS_IB_DIRECT

#define HSIO_S6G_PLL_STATUS_PLL_CAL_NOT_DONE
#define HSIO_S6G_PLL_STATUS_PLL_CAL_ERR
#define HSIO_S6G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR
#define HSIO_S6G_PLL_STATUS_PLL_RB_DATA(x)
#define HSIO_S6G_PLL_STATUS_PLL_RB_DATA_M

#define HSIO_S6G_REVID_SERDES_REV(x)
#define HSIO_S6G_REVID_SERDES_REV_M
#define HSIO_S6G_REVID_SERDES_REV_X(x)
#define HSIO_S6G_REVID_RCPLL_REV(x)
#define HSIO_S6G_REVID_RCPLL_REV_M
#define HSIO_S6G_REVID_RCPLL_REV_X(x)
#define HSIO_S6G_REVID_SER_REV(x)
#define HSIO_S6G_REVID_SER_REV_M
#define HSIO_S6G_REVID_SER_REV_X(x)
#define HSIO_S6G_REVID_DES_REV(x)
#define HSIO_S6G_REVID_DES_REV_M
#define HSIO_S6G_REVID_DES_REV_X(x)
#define HSIO_S6G_REVID_OB_REV(x)
#define HSIO_S6G_REVID_OB_REV_M
#define HSIO_S6G_REVID_OB_REV_X(x)
#define HSIO_S6G_REVID_IB_REV(x)
#define HSIO_S6G_REVID_IB_REV_M

#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_WR_ONE_SHOT
#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_RD_ONE_SHOT
#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR(x)
#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR_M

#define HSIO_HW_CFG_DEV2G5_10_MODE
#define HSIO_HW_CFG_DEV1G_9_MODE
#define HSIO_HW_CFG_DEV1G_6_MODE
#define HSIO_HW_CFG_DEV1G_5_MODE
#define HSIO_HW_CFG_DEV1G_4_MODE
#define HSIO_HW_CFG_PCIE_ENA
#define HSIO_HW_CFG_QSGMII_ENA

#define HSIO_HW_QSGMII_CFG_SHYST_DIS
#define HSIO_HW_QSGMII_CFG_E_DET_ENA
#define HSIO_HW_QSGMII_CFG_USE_I1_ENA
#define HSIO_HW_QSGMII_CFG_FLIP_LANES

#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS(x)
#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_M
#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_X(x)
#define HSIO_HW_QSGMII_STAT_SYNC

#define HSIO_CLK_CFG_CLKDIV_PHY(x)
#define HSIO_CLK_CFG_CLKDIV_PHY_M
#define HSIO_CLK_CFG_CLKDIV_PHY_X(x)
#define HSIO_CLK_CFG_CLKDIV_PHY_DIS

#define HSIO_TEMP_SENSOR_CTRL_FORCE_TEMP_RD
#define HSIO_TEMP_SENSOR_CTRL_FORCE_RUN
#define HSIO_TEMP_SENSOR_CTRL_FORCE_NO_RST
#define HSIO_TEMP_SENSOR_CTRL_FORCE_POWER_UP
#define HSIO_TEMP_SENSOR_CTRL_FORCE_CLK
#define HSIO_TEMP_SENSOR_CTRL_SAMPLE_ENA

#define HSIO_TEMP_SENSOR_CFG_RUN_WID(x)
#define HSIO_TEMP_SENSOR_CFG_RUN_WID_M
#define HSIO_TEMP_SENSOR_CFG_RUN_WID_X(x)
#define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER(x)
#define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER_M

#define HSIO_TEMP_SENSOR_STAT_TEMP_VALID
#define HSIO_TEMP_SENSOR_STAT_TEMP(x)
#define HSIO_TEMP_SENSOR_STAT_TEMP_M

#endif