// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved. */ #include <linux/clk.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/nvmem-consumer.h> #include <linux/of.h> #include <linux/phy/phy.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> #include <linux/reset.h> #include <linux/slab.h> #include <dt-bindings/phy/phy-qcom-qusb2.h> #define QUSB2PHY_PLL … #define QUSB2PHY_PLL_TEST … #define CLK_REF_SEL … #define QUSB2PHY_PLL_TUNE … #define QUSB2PHY_PLL_USER_CTL1 … #define QUSB2PHY_PLL_USER_CTL2 … #define QUSB2PHY_PLL_AUTOPGM_CTL1 … #define QUSB2PHY_PLL_PWR_CTRL … /* QUSB2PHY_PLL_STATUS register bits */ #define PLL_LOCKED … /* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */ #define CORE_READY_STATUS … /* QUSB2PHY_PORT_POWERDOWN register bits */ #define CLAMP_N_EN … #define FREEZIO_N … #define POWER_DOWN … /* QUSB2PHY_PWR_CTRL1 register bits */ #define PWR_CTRL1_VREF_SUPPLY_TRIM … #define PWR_CTRL1_CLAMP_N_EN … #define QUSB2PHY_REFCLK_ENABLE … #define PHY_CLK_SCHEME_SEL … /* QUSB2PHY_INTR_CTRL register bits */ #define DMSE_INTR_HIGH_SEL … #define DPSE_INTR_HIGH_SEL … #define CHG_DET_INTR_EN … #define DMSE_INTR_EN … #define DPSE_INTR_EN … /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */ #define CORE_PLL_EN_FROM_RESET … #define CORE_RESET … #define CORE_RESET_MUX … /* QUSB2PHY_IMP_CTRL1 register bits */ #define IMP_RES_OFFSET_MASK … #define IMP_RES_OFFSET_SHIFT … /* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */ #define BIAS_CTRL2_RES_OFFSET_MASK … #define BIAS_CTRL2_RES_OFFSET_SHIFT … /* QUSB2PHY_CHG_CONTROL_2 register bits */ #define CHG_CTRL2_OFFSET_MASK … #define CHG_CTRL2_OFFSET_SHIFT … /* QUSB2PHY_PORT_TUNE1 register bits */ #define HSTX_TRIM_MASK … #define HSTX_TRIM_SHIFT … #define PREEMPH_WIDTH_HALF_BIT … #define PREEMPHASIS_EN_MASK … #define PREEMPHASIS_EN_SHIFT … /* QUSB2PHY_PORT_TUNE2 register bits */ #define HSDISC_TRIM_MASK … #define HSDISC_TRIM_SHIFT … #define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO … #define QUSB2PHY_PLL_CLOCK_INVERTERS … #define QUSB2PHY_PLL_CMODE … #define QUSB2PHY_PLL_LOCK_DELAY … #define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO … #define QUSB2PHY_PLL_BIAS_CONTROL_1 … #define QUSB2PHY_PLL_BIAS_CONTROL_2 … #define QUSB2PHY_PWR_CTRL2 … #define QUSB2PHY_IMP_CTRL1 … #define QUSB2PHY_IMP_CTRL2 … #define QUSB2PHY_CHG_CTRL2 … struct qusb2_phy_init_tbl { … }; #define QUSB2_PHY_INIT_CFG(o, v) … #define QUSB2_PHY_INIT_CFG_L(o, v) … /* set of registers with offsets different per-PHY */ enum qusb2phy_reg_layout { … }; static const struct qusb2_phy_init_tbl ipq6018_init_tbl[] = …; static const unsigned int ipq6018_regs_layout[] = …; static const unsigned int msm8996_regs_layout[] = …; static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = …; static const unsigned int msm8998_regs_layout[] = …; static const struct qusb2_phy_init_tbl msm8998_init_tbl[] = …; static const struct qusb2_phy_init_tbl sm6115_init_tbl[] = …; static const unsigned int qusb2_v2_regs_layout[] = …; static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = …; struct qusb2_phy_cfg { … }; static const struct qusb2_phy_cfg msm8996_phy_cfg = …; static const struct qusb2_phy_cfg msm8998_phy_cfg = …; static const struct qusb2_phy_cfg ipq6018_phy_cfg = …; static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = …; static const struct qusb2_phy_cfg sdm660_phy_cfg = …; static const struct qusb2_phy_cfg sm6115_phy_cfg = …; static const char * const qusb2_phy_vreg_names[] = …; #define QUSB2_NUM_VREGS … /* struct override_param - structure holding qusb2 v2 phy overriding param * set override true if the device tree property exists and read and assign * to value */ struct override_param { … }; /*struct override_params - structure holding qusb2 v2 phy overriding params * @imp_res_offset: rescode offset to be updated in IMP_CTRL1 register * @hstx_trim: HSTX_TRIM to be updated in TUNE1 register * @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1 * @bias_ctrl: bias ctrl to be updated in BIAS_CONTROL_2 register * @charge_ctrl: charge ctrl to be updated in CHG_CTRL2 register * @hsdisc_trim: disconnect threshold to be updated in TUNE2 register */ struct override_params { … }; /** * struct qusb2_phy - structure holding qusb2 phy attributes * * @phy: generic phy * @base: iomapped memory space for qubs2 phy * * @cfg_ahb_clk: AHB2PHY interface clock * @ref_clk: phy reference clock * @iface_clk: phy interface clock * @phy_reset: phy reset control * @vregs: regulator supplies bulk data * * @tcsr: TCSR syscon register map * @cell: nvmem cell containing phy tuning value * * @overrides: pointer to structure for all overriding tuning params * * @cfg: phy config data * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme * @phy_initialized: indicate if PHY has been initialized * @mode: current PHY mode */ struct qusb2_phy { … }; static inline void qusb2_write_mask(void __iomem *base, u32 offset, u32 val, u32 mask) { … } static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val) { … } static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val) { … } static inline void qcom_qusb2_phy_configure(void __iomem *base, const unsigned int *regs, const struct qusb2_phy_init_tbl tbl[], int num) { … } /* * Update board specific PHY tuning override values if specified from * device tree. */ static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy) { … } /* * Fetches HS Tx tuning value from nvmem and sets the * QUSB2PHY_PORT_TUNE1/2 register. * For error case, skip setting the value and use the default value. */ static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy) { … } static int qusb2_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) { … } static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev) { … } static int __maybe_unused qusb2_phy_runtime_resume(struct device *dev) { … } static int qusb2_phy_init(struct phy *phy) { … } static int qusb2_phy_exit(struct phy *phy) { … } static const struct phy_ops qusb2_phy_gen_ops = …; static const struct of_device_id qusb2_phy_of_match_table[] = …; MODULE_DEVICE_TABLE(of, qusb2_phy_of_match_table); static const struct dev_pm_ops qusb2_phy_pm_ops = …; static int qusb2_phy_probe(struct platform_device *pdev) { … } static struct platform_driver qusb2_phy_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
Codebase Browser
linux