/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. */ #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_5NM_H_ #define QCOM_PHY_QMP_QSERDES_TXRX_V5_5NM_H_ /* Only for QMP V5 5NM PHY - TX registers */ #define QSERDES_V5_5NM_TX_BIST_MODE_LANENO … #define QSERDES_V5_5NM_TX_BIST_INVERT … #define QSERDES_V5_5NM_TX_CLKBUF_ENABLE … #define QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL … #define QSERDES_V5_5NM_TX_TX_IDLE_LVL_LARGE_AMP … #define QSERDES_V5_5NM_TX_TX_DRV_LVL … #define QSERDES_V5_5NM_TX_TX_DRV_LVL_OFFSET … #define QSERDES_V5_5NM_TX_RESET_TSYNC_EN … #define QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN … #define QSERDES_V5_5NM_TX_LPB_EN … #define QSERDES_V5_5NM_TX_RES_CODE_LANE_TX … #define QSERDES_V5_5NM_TX_RES_CODE_LANE_RX … #define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX … #define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX … #define QSERDES_V5_5NM_TX_PERL_LENGTH1 … #define QSERDES_V5_5NM_TX_PERL_LENGTH2 … #define QSERDES_V5_5NM_TX_SERDES_BYP_EN_OUT … #define QSERDES_V5_5NM_TX_DEBUG_BUS_SEL … #define QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN … #define QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN … #define QSERDES_V5_5NM_TX_TX_POL_INV … #define QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN … #define QSERDES_V5_5NM_TX_BIST_PATTERN1 … #define QSERDES_V5_5NM_TX_BIST_PATTERN2 … #define QSERDES_V5_5NM_TX_BIST_PATTERN3 … #define QSERDES_V5_5NM_TX_BIST_PATTERN4 … #define QSERDES_V5_5NM_TX_BIST_PATTERN5 … #define QSERDES_V5_5NM_TX_BIST_PATTERN6 … #define QSERDES_V5_5NM_TX_BIST_PATTERN7 … #define QSERDES_V5_5NM_TX_BIST_PATTERN8 … #define QSERDES_V5_5NM_TX_LANE_MODE_1 … #define QSERDES_V5_5NM_TX_LANE_MODE_2 … #define QSERDES_V5_5NM_TX_LANE_MODE_3 … #define QSERDES_V5_5NM_TX_ATB_SEL1 … #define QSERDES_V5_5NM_TX_ATB_SEL2 … #define QSERDES_V5_5NM_TX_RCV_DETECT_LVL … #define QSERDES_V5_5NM_TX_RCV_DETECT_LVL_2 … #define QSERDES_V5_5NM_TX_PRBS_SEED1 … #define QSERDES_V5_5NM_TX_PRBS_SEED2 … #define QSERDES_V5_5NM_TX_PRBS_SEED3 … #define QSERDES_V5_5NM_TX_PRBS_SEED4 … #define QSERDES_V5_5NM_TX_RESET_GEN … #define QSERDES_V5_5NM_TX_RESET_GEN_MUXES … #define QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN … #define QSERDES_V5_5NM_TX_VMODE_CTRL1 … #define QSERDES_V5_5NM_TX_ALOG_OBSV_BUS_CTRL_1 … #define QSERDES_V5_5NM_TX_BIST_STATUS … #define QSERDES_V5_5NM_TX_BIST_ERROR_COUNT1 … #define QSERDES_V5_5NM_TX_BIST_ERROR_COUNT2 … #define QSERDES_V5_5NM_TX_ALOG_OBSV_BUS_STATUS_1 … #define QSERDES_V5_5NM_TX_LANE_DIG_CONFIG … #define QSERDES_V5_5NM_TX_PI_QEC_CTRL … #define QSERDES_V5_5NM_TX_PRE_EMPH … #define QSERDES_V5_5NM_TX_SW_RESET … #define QSERDES_V5_5NM_TX_TX_BAND … #define QSERDES_V5_5NM_TX_SLEW_CNTL0 … #define QSERDES_V5_5NM_TX_SLEW_CNTL1 … #define QSERDES_V5_5NM_TX_INTERFACE_SELECT … #define QSERDES_V5_5NM_TX_DIG_BKUP_CTRL … #define QSERDES_V5_5NM_TX_DEBUG_BUS0 … #define QSERDES_V5_5NM_TX_DEBUG_BUS1 … #define QSERDES_V5_5NM_TX_DEBUG_BUS2 … #define QSERDES_V5_5NM_TX_DEBUG_BUS3 … #define QSERDES_V5_5NM_TX_TX_BKUP_RO_BUS … /* Only for QMP V5 5NM PHY - RX registers */ #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE0 … #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE1 … #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 … #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE3 … #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE0 … #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE1 … #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE2 … #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE3 … #define QSERDES_V5_5NM_RX_UCDR_SO_SATURATION … #define QSERDES_V5_5NM_RX_UCDR_FO_TO_SO_DELAY … #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE0 … #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE0 … #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE1 … #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE1 … #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE2 … #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE2 … #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE3 … #define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE3 … #define QSERDES_V5_5NM_RX_UCDR_PI_CTRL1 … #define QSERDES_V5_5NM_RX_UCDR_PI_CTRL2 … #define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH1_RATE0 … #define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH1_RATE1 … #define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH1_RATE2 … #define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH1_RATE3 … #define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH2_RATE0 … #define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH2_RATE1 … #define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH2_RATE2 … #define QSERDES_V5_5NM_RX_UCDR_SB2_THRESH2_RATE3 … #define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN1_RATE0 … #define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN1_RATE1 … #define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN1_RATE2 … #define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN1_RATE3 … #define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE0 … #define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE1 … #define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2 … #define QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE3 … #define QSERDES_V5_5NM_RX_RXCLK_DIV2_CTRL … #define QSERDES_V5_5NM_RX_RX_BAND … #define QSERDES_V5_5NM_RX_RX_TERM_BW … #define QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE0 … #define QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE1 … #define QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2 … #define QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE3 … #define QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE0 … #define QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE1 … #define QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2 … #define QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE3 … #define QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS … #define QSERDES_V5_5NM_RX_UCDR_PD_DATA_FILTER_ENABLES … #define QSERDES_V5_5NM_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE0 … #define QSERDES_V5_5NM_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE1 … #define QSERDES_V5_5NM_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE2 … #define QSERDES_V5_5NM_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 … #define QSERDES_V5_5NM_RX_AUX_CONTROL … #define QSERDES_V5_5NM_RX_AUXDATA_TB … #define QSERDES_V5_5NM_RX_RCLK_AUXDATA_SEL … #define QSERDES_V5_5NM_RX_EOM_CTRL … #define QSERDES_V5_5NM_RX_AC_JTAG_ENABLE … #define QSERDES_V5_5NM_RX_AC_JTAG_INITP … #define QSERDES_V5_5NM_RX_AC_JTAG_INITN … #define QSERDES_V5_5NM_RX_AC_JTAG_LVL … #define QSERDES_V5_5NM_RX_AC_JTAG_MODE … #define QSERDES_V5_5NM_RX_AC_JTAG_RESET … #define QSERDES_V5_5NM_RX_RX_RCVR_IQ_EN … #define QSERDES_V5_5NM_RX_RX_Q_EN_RATES … #define QSERDES_V5_5NM_RX_RX_IDAC_I0_DC_OFFSETS … #define QSERDES_V5_5NM_RX_RX_IDAC_I0BAR_DC_OFFSETS … #define QSERDES_V5_5NM_RX_RX_IDAC_I1_DC_OFFSETS … #define QSERDES_V5_5NM_RX_RX_IDAC_I1BAR_DC_OFFSETS … #define QSERDES_V5_5NM_RX_RX_IDAC_Q_DC_OFFSETS … #define QSERDES_V5_5NM_RX_RX_IDAC_QBAR_DC_OFFSETS … #define QSERDES_V5_5NM_RX_RX_IDAC_A_DC_OFFSETS … #define QSERDES_V5_5NM_RX_RX_IDAC_ABAR_DC_OFFSETS … #define QSERDES_V5_5NM_RX_RX_IDAC_EN … #define QSERDES_V5_5NM_RX_RX_IDAC_ENABLES … #define QSERDES_V5_5NM_RX_RX_IDAC_SIGN … #define QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE … #define QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL1 … #define QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2 … #define QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET … #define QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE … #define QSERDES_V5_5NM_RX_RX_HIGHZ_PARRATE … #define QSERDES_V5_5NM_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET … #define QSERDES_V5_5NM_RX_DFE_1 … #define QSERDES_V5_5NM_RX_DFE_2 … #define QSERDES_V5_5NM_RX_DFE_3 … #define QSERDES_V5_5NM_RX_DFE_4 … #define QSERDES_V5_5NM_RX_DFE_TAP3_CTRL … #define QSERDES_V5_5NM_RX_DFE_TAP3_MANVAL_KTAP … #define QSERDES_V5_5NM_RX_DFE_TAP4_CTRL … #define QSERDES_V5_5NM_RX_DFE_TAP4_MANVAL_KTAP … #define QSERDES_V5_5NM_RX_DFE_TAP5_CTRL … #define QSERDES_V5_5NM_RX_DFE_TAP5_MANVAL_KTAP … #define QSERDES_V5_5NM_RX_TX_ADPT_CTRL … #define QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1 … #define QSERDES_V5_5NM_RX_DFE_DAC_ENABLE2 … #define QSERDES_V5_5NM_RX_TX_ADAPT_PRE_THRESH1 … #define QSERDES_V5_5NM_RX_TX_ADAPT_PRE_THRESH2 … #define QSERDES_V5_5NM_RX_TX_ADAPT_POST_THRESH1 … #define QSERDES_V5_5NM_RX_TX_ADAPT_POST_THRESH2 … #define QSERDES_V5_5NM_RX_TX_ADAPT_MAIN_THRESH1 … #define QSERDES_V5_5NM_RX_TX_ADAPT_MAIN_THRESH2 … #define QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1 … #define QSERDES_V5_5NM_RX_VGA_CAL_CNTRL2 … #define QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL … #define QSERDES_V5_5NM_RX_VTHRESH_CAL_CNTRL1 … #define QSERDES_V5_5NM_RX_VTHRESH_CAL_CNTRL2 … #define QSERDES_V5_5NM_RX_VTHRESH_CAL_MAN_VAL_RATE0 … #define QSERDES_V5_5NM_RX_VTHRESH_CAL_MAN_VAL_RATE1 … #define QSERDES_V5_5NM_RX_VTHRESH_CAL_MAN_VAL_RATE2 … #define QSERDES_V5_5NM_RX_VTHRESH_CAL_MAN_VAL_RATE3 … #define QSERDES_V5_5NM_RX_GM_CAL … #define QSERDES_V5_5NM_RX_RX_VGA_GAIN2_BLK1 … #define QSERDES_V5_5NM_RX_RX_VGA_GAIN2_BLK2 … #define QSERDES_V5_5NM_RX_RX_EQU_ADAPTOR_CNTRL2 … #define QSERDES_V5_5NM_RX_RX_EQU_ADAPTOR_CNTRL3 … #define QSERDES_V5_5NM_RX_RX_EQU_ADAPTOR_CNTRL4 … #define QSERDES_V5_5NM_RX_RX_IDAC_TSETTLE_LOW … #define QSERDES_V5_5NM_RX_RX_EQ_OFFSET_LSB … #define QSERDES_V5_5NM_RX_RX_EQ_OFFSET_MSB … #define QSERDES_V5_5NM_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 … #define QSERDES_V5_5NM_RX_RX_OFFSET_ADAPTOR_CNTRL2 … #define QSERDES_V5_5NM_RX_SIGDET_ENABLES … #define QSERDES_V5_5NM_RX_SIGDET_CNTRL … #define QSERDES_V5_5NM_RX_SIGDET_LVL … #define QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL … #define QSERDES_V5_5NM_RX_CDR_FREEZE_UP_DN … #define QSERDES_V5_5NM_RX_CDR_RESET_OVERRIDE … #define QSERDES_V5_5NM_RX_RX_INTERFACE_MODE … #define QSERDES_V5_5NM_RX_JITTER_GEN_MODE … #define QSERDES_V5_5NM_RX_SJ_AMP1 … #define QSERDES_V5_5NM_RX_SJ_AMP2 … #define QSERDES_V5_5NM_RX_SJ_PER1 … #define QSERDES_V5_5NM_RX_SJ_PER2 … #define QSERDES_V5_5NM_RX_PPM_OFFSET1 … #define QSERDES_V5_5NM_RX_PPM_OFFSET2 … #define QSERDES_V5_5NM_RX_SIGN_PPM_PERIOD1 … #define QSERDES_V5_5NM_RX_SIGN_PPM_PERIOD2 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B0 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B1 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B2 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B3 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B4 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B5 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B6 … #define QSERDES_V5_5NM_RX_RX_MODE_RATE3_B7 … #define QSERDES_V5_5NM_RX_PHPRE_CTRL … #define QSERDES_V5_5NM_RX_PHPRE_INITVAL … #define QSERDES_V5_5NM_RX_DFE_EN_TIMER … #define QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET … #define QSERDES_V5_5NM_RX_DCC_CTRL1 … #define QSERDES_V5_5NM_RX_DCC_CTRL2 … #define QSERDES_V5_5NM_RX_DCC_OFFSET … #define QSERDES_V5_5NM_RX_DCC_CMUX_POSTCAL_OFFSET … #define QSERDES_V5_5NM_RX_DCC_CMUX_CAL_CTRL1 … #define QSERDES_V5_5NM_RX_DCC_CMUX_CAL_CTRL2 … #define QSERDES_V5_5NM_RX_ALOG_OBSV_BUS_CTRL_1 … #define QSERDES_V5_5NM_RX_RX_MARG_CTRL1 … #define QSERDES_V5_5NM_RX_RX_MARG_CTRL2 … #define QSERDES_V5_5NM_RX_RX_MARG_CTRL3 … #define QSERDES_V5_5NM_RX_RX_MARG_CTRL_4 … #define QSERDES_V5_5NM_RX_RX_MARG_CFG_RATE_0_1 … #define QSERDES_V5_5NM_RX_RX_MARG_CFG_RATE_2_3 … #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_CTRL1 … #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_CTRL2 … #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH1_RATE210 … #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH1_RATE3 … #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH2_RATE210 … #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH2_RATE3 … #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH3_RATE210 … #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH3_RATE3 … #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH4_RATE210 … #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH4_RATE3 … #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH5_RATE210 … #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH5_RATE3 … #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH6_RATE210 … #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH6_RATE3 … #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH7_RATE210 … #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_THRESH7_RATE3 … #define QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE10 … #define QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32 … #define QSERDES_V5_5NM_RX_RX_MARG_VERTICAL_CTRL … #define QSERDES_V5_5NM_RX_RX_MARG_VERTICAL_CODE … #define QSERDES_V5_5NM_RX_RES_CODE_THRESH_HIGH_AND_BYP … #define QSERDES_V5_5NM_RX_RES_CODE_THRESH_LOW … #define QSERDES_V5_5NM_RX_RX_BKUP_CTRL1 … #define QSERDES_V5_5NM_RX_RX_BKUP_CTRL2 … #define QSERDES_V5_5NM_RX_RX_BKUP_CTRL3 … #define QSERDES_V5_5NM_RX_PI_CTRL1 … #define QSERDES_V5_5NM_RX_PI_CTRL2 … #define QSERDES_V5_5NM_RX_PI_QUAD … #define QSERDES_V5_5NM_RX_QPI_CTRL1 … #define QSERDES_V5_5NM_RX_QPI_CTRL2 … #define QSERDES_V5_5NM_RX_QPI_QUAD … #define QSERDES_V5_5NM_RX_IDATA1 … #define QSERDES_V5_5NM_RX_IDATA2 … #define QSERDES_V5_5NM_RX_IDATA3 … #define QSERDES_V5_5NM_RX_AC_JTAG_OUTP … #define QSERDES_V5_5NM_RX_AC_JTAG_OUTN … #define QSERDES_V5_5NM_RX_RX_SIGDET … #define QSERDES_V5_5NM_RX_ALOG_OBSV_BUS_STATUS_1 … #define QSERDES_V5_5NM_RX_READ_EQCODE … #define QSERDES_V5_5NM_RX_READ_OFFSETCODE … #define QSERDES_V5_5NM_RX_IA_ERROR_COUNTER_LOW … #define QSERDES_V5_5NM_RX_IA_ERROR_COUNTER_HIGH … #define QSERDES_V5_5NM_RX_VGA_READ_CODE … #define QSERDES_V5_5NM_RX_VTHRESH_READ_CODE … #define QSERDES_V5_5NM_RX_DFE_TAP1_READ_CODE … #define QSERDES_V5_5NM_RX_DFE_TAP2_READ_CODE … #define QSERDES_V5_5NM_RX_DFE_TAP3_READ_CODE … #define QSERDES_V5_5NM_RX_DFE_TAP4_READ_CODE … #define QSERDES_V5_5NM_RX_DFE_TAP5_READ_CODE … #define QSERDES_V5_5NM_RX_IDAC_STATUS_I0 … #define QSERDES_V5_5NM_RX_IDAC_STATUS_I0BAR … #define QSERDES_V5_5NM_RX_IDAC_STATUS_I1 … #define QSERDES_V5_5NM_RX_IDAC_STATUS_I1BAR … #define QSERDES_V5_5NM_RX_IDAC_STATUS_Q … #define QSERDES_V5_5NM_RX_IDAC_STATUS_QBAR … #define QSERDES_V5_5NM_RX_IDAC_STATUS_A … #define QSERDES_V5_5NM_RX_IDAC_STATUS_ABAR … #define QSERDES_V5_5NM_RX_IDAC_STATUS_SM_ON … #define QSERDES_V5_5NM_RX_IDAC_STATUS_SIGNERROR … #define QSERDES_V5_5NM_RX_IVCM_CAL_STATUS … #define QSERDES_V5_5NM_RX_IVCM_CAL_DEBUG_STATUS … #define QSERDES_V5_5NM_RX_DCC_CAL_STATUS … #define QSERDES_V5_5NM_RX_DCC_READ_CODE_STATUS … #define QSERDES_V5_5NM_RX_RX_MARG_DEBUG1_STATUS … #define QSERDES_V5_5NM_RX_RX_MARG_DEBUG2_STATUS … #define QSERDES_V5_5NM_RX_RX_MARG_READ_CODE_STATUS … #define QSERDES_V5_5NM_RX_EOM_ERR_CNT_LSB_STATUS … #define QSERDES_V5_5NM_RX_EOM_ERR_CNT_MSB_STATUS … #define QSERDES_V5_5NM_RX_RX_MARG_COARSE_TUNE_STATUS … #define QSERDES_V5_5NM_RX_RX_BKUP_READ_BUS1_STATUS … #define QSERDES_V5_5NM_RX_RX_BKUP_READ_BUS2_STATUS … #define QSERDES_V5_5NM_RX_RX_BKUP_READ_BUS3_STATUS … #endif
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