#ifndef QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_
#define QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_
#define QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL …
#define QSERDES_V6_LN_SHRD_RX_Q_EN_RATES …
#define QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1 …
#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1 …
#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2 …
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0 …
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1 …
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2 …
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3 …
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4 …
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5 …
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6 …
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210 …
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3 …
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210 …
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3 …
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210 …
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3 …
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3 …
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3 …
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3 …
#define QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE …
#endif