#ifndef QCOM_PHY_QMP_PCS_V5_H_
#define QCOM_PHY_QMP_PCS_V5_H_
#define QPHY_V5_PCS_SW_RESET …
#define QPHY_V5_PCS_PCS_STATUS1 …
#define QPHY_V5_PCS_POWER_DOWN_CONTROL …
#define QPHY_V5_PCS_START_CONTROL …
#define QPHY_V5_PCS_LOCK_DETECT_CONFIG1 …
#define QPHY_V5_PCS_LOCK_DETECT_CONFIG2 …
#define QPHY_V5_PCS_LOCK_DETECT_CONFIG3 …
#define QPHY_V5_PCS_LOCK_DETECT_CONFIG6 …
#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 …
#define QPHY_V5_PCS_G3S2_PRE_GAIN …
#define QPHY_V5_PCS_RX_SIGDET_LVL …
#define QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L …
#define QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H …
#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 …
#define QPHY_V5_PCS_CDR_RESET_TIME …
#define QPHY_V5_PCS_RX_CONFIG …
#define QPHY_V5_PCS_ALIGN_DETECT_CONFIG1 …
#define QPHY_V5_PCS_ALIGN_DETECT_CONFIG2 …
#define QPHY_V5_PCS_PCS_TX_RX_CONFIG …
#define QPHY_V5_PCS_EQ_CONFIG1 …
#define QPHY_V5_PCS_EQ_CONFIG2 …
#define QPHY_V5_PCS_EQ_CONFIG3 …
#define QPHY_V5_PCS_EQ_CONFIG5 …
#endif