linux/drivers/phy/qualcomm/phy-qcom-qmp-combo.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/usb/typec.h>
#include <linux/usb/typec_mux.h>

#include <drm/bridge/aux-bridge.h>

#include <dt-bindings/phy/phy-qcom-qmp.h>

#include "phy-qcom-qmp-common.h"

#include "phy-qcom-qmp.h"
#include "phy-qcom-qmp-pcs-misc-v3.h"
#include "phy-qcom-qmp-pcs-usb-v4.h"
#include "phy-qcom-qmp-pcs-usb-v5.h"
#include "phy-qcom-qmp-pcs-usb-v6.h"

#include "phy-qcom-qmp-dp-com-v3.h"

#include "phy-qcom-qmp-dp-phy.h"
#include "phy-qcom-qmp-dp-phy-v3.h"
#include "phy-qcom-qmp-dp-phy-v4.h"
#include "phy-qcom-qmp-dp-phy-v5.h"
#include "phy-qcom-qmp-dp-phy-v6.h"

/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
/* DP PHY soft reset */
#define SW_DPPHY_RESET
/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
#define SW_DPPHY_RESET_MUX
/* USB3 PHY soft reset */
#define SW_USB3PHY_RESET
/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
#define SW_USB3PHY_RESET_MUX

/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
#define USB3_MODE
#define DP_MODE

/* QPHY_V3_DP_COM_TYPEC_CTRL register bits */
#define SW_PORTSELECT_VAL
#define SW_PORTSELECT_MUX

#define PHY_INIT_COMPLETE_TIMEOUT

/* set of registers with offsets different per-PHY */
enum qphy_reg_layout {};

static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] =;

static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] =;

static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] =;

static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] =;

static const unsigned int qmp_v6_n4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] =;

static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] =;

static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] =;

static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] =;

static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] =;

static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] =;

static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] =;

static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] =;

static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] =;

static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] =;

static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] =;

static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] =;

static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] =;

static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] =;

static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] =;

static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] =;

static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] =;

static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] =;

static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] =;

static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] =;

static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] =;

static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] =;

static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] =;

static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] =;

static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] =;

static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] =;

static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] =;

static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] =;

static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] =;

static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] =;

static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] =;

static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] =;

static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] =;

static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] =;

static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] =;

static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] =;

static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] =;

static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] =;

static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] =;

static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] =;

static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] =;

static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl[] =;

static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] =;

static const struct qmp_phy_init_tbl qmp_v6_n4_dp_tx_tbl[] =;

static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] =;

static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] =;

static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] =;

static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] =;

static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_rbr[] =;

static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr[] =;

static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr2[] =;

static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr3[] =;

static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] =;

static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] =;

static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] =;

static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] =;

static const struct qmp_phy_init_tbl x1e80100_usb43dp_serdes_tbl[] =;

static const struct qmp_phy_init_tbl x1e80100_usb43dp_tx_tbl[] =;

static const struct qmp_phy_init_tbl x1e80100_usb43dp_rx_tbl[] =;

static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_tbl[] =;

static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] =;

/* list of regulators */
struct qmp_regulator_data {};

static struct qmp_regulator_data qmp_phy_vreg_l[] =;

static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] =;

static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] =;

static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] =;

static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] =;

static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] =;

static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] =;

static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] =;

static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] =;

static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] =;

static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] =;

static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] =;

static const u8 qmp_dp_v6_voltage_swing_hbr_rbr[4][4] =;

static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] =;

struct qmp_combo;

struct qmp_combo_offsets {};

struct qmp_phy_cfg {};

struct qmp_combo {};

static void qmp_v3_dp_aux_init(struct qmp_combo *qmp);
static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp);
static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp);
static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp);

static void qmp_v4_dp_aux_init(struct qmp_combo *qmp);
static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp);
static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp);
static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp);

static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
{}

static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
{}

/* list of clocks required by phy */
static const char * const qmp_combo_phy_clk_l[] =;

/* list of resets */
static const char * const msm8996_usb3phy_reset_l[] =;

static const char * const sc7180_usb3phy_reset_l[] =;

static const struct qmp_combo_offsets qmp_combo_offsets_v3 =;

static const struct qmp_combo_offsets qmp_combo_offsets_v5 =;

static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg =;

static const struct qmp_phy_cfg sdm845_usb3dpphy_cfg =;

static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg =;

static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg =;

static const struct qmp_phy_cfg x1e80100_usb3dpphy_cfg =;

static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg =;

static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg =;

static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg =;

static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg =;

static const struct qmp_phy_cfg sm8650_usb3dpphy_cfg =;

static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp)
{}

static void qmp_v3_dp_aux_init(struct qmp_combo *qmp)
{}

static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp)
{}

static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp)
{}

static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp)
{}

static int qmp_combo_configure_dp_clocks(struct qmp_combo *qmp)
{}

static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp)
{}

/*
 * We need to calibrate the aux setting here as many times
 * as the caller tries
 */
static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp)
{}

static void qmp_v4_dp_aux_init(struct qmp_combo *qmp)
{}

static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp)
{}

static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp)
{}

static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp)
{}

/*
 * We need to calibrate the aux setting here as many times
 * as the caller tries
 */
static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp)
{}

static int qmp_combo_dp_configure(struct phy *phy, union phy_configure_opts *opts)
{}

static int qmp_combo_dp_calibrate(struct phy *phy)
{}

static int qmp_combo_com_init(struct qmp_combo *qmp, bool force)
{}

static int qmp_combo_com_exit(struct qmp_combo *qmp, bool force)
{}

static int qmp_combo_dp_init(struct phy *phy)
{}

static int qmp_combo_dp_exit(struct phy *phy)
{}

static int qmp_combo_dp_power_on(struct phy *phy)
{}

static int qmp_combo_dp_power_off(struct phy *phy)
{}

static int qmp_combo_usb_power_on(struct phy *phy)
{}

static int qmp_combo_usb_power_off(struct phy *phy)
{}

static int qmp_combo_usb_init(struct phy *phy)
{}

static int qmp_combo_usb_exit(struct phy *phy)
{}

static int qmp_combo_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode)
{}

static const struct phy_ops qmp_combo_usb_phy_ops =;

static const struct phy_ops qmp_combo_dp_phy_ops =;

static void qmp_combo_enable_autonomous_mode(struct qmp_combo *qmp)
{}

static void qmp_combo_disable_autonomous_mode(struct qmp_combo *qmp)
{}

static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev)
{}

static int __maybe_unused qmp_combo_runtime_resume(struct device *dev)
{}

static const struct dev_pm_ops qmp_combo_pm_ops =;

static int qmp_combo_vreg_init(struct qmp_combo *qmp)
{}

static int qmp_combo_reset_init(struct qmp_combo *qmp)
{}

static int qmp_combo_clk_init(struct qmp_combo *qmp)
{}

static void phy_clk_release_provider(void *res)
{}

/*
 * Register a fixed rate pipe clock.
 *
 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
 * controls it. The <s>_pipe_clk coming out of the GCC is requested
 * by the PHY driver for its operations.
 * We register the <s>_pipe_clksrc here. The gcc driver takes care
 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
 * Below picture shows this relationship.
 *
 *         +---------------+
 *         |   PHY block   |<<---------------------------------------+
 *         |               |                                         |
 *         |   +-------+   |                   +-----+               |
 *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
 *    clk  |   +-------+   |                   +-----+
 *         +---------------+
 */
static int phy_pipe_clk_register(struct qmp_combo *qmp, struct device_node *np)
{}

/*
 * Display Port PLL driver block diagram for branch clocks
 *
 *              +------------------------------+
 *              |         DP_VCO_CLK           |
 *              |                              |
 *              |    +-------------------+     |
 *              |    |   (DP PLL/VCO)    |     |
 *              |    +---------+---------+     |
 *              |              v               |
 *              |   +----------+-----------+   |
 *              |   | hsclk_divsel_clk_src |   |
 *              |   +----------+-----------+   |
 *              +------------------------------+
 *                              |
 *          +---------<---------v------------>----------+
 *          |                                           |
 * +--------v----------------+                          |
 * |    dp_phy_pll_link_clk  |                          |
 * |     link_clk            |                          |
 * +--------+----------------+                          |
 *          |                                           |
 *          |                                           |
 *          v                                           v
 * Input to DISPCC block                                |
 * for link clk, crypto clk                             |
 * and interface clock                                  |
 *                                                      |
 *                                                      |
 *      +--------<------------+-----------------+---<---+
 *      |                     |                 |
 * +----v---------+  +--------v-----+  +--------v------+
 * | vco_divided  |  | vco_divided  |  | vco_divided   |
 * |    _clk_src  |  |    _clk_src  |  |    _clk_src   |
 * |              |  |              |  |               |
 * |divsel_six    |  |  divsel_two  |  |  divsel_four  |
 * +-------+------+  +-----+--------+  +--------+------+
 *         |                 |                  |
 *         v---->----------v-------------<------v
 *                         |
 *              +----------+-----------------+
 *              |   dp_phy_pll_vco_div_clk   |
 *              +---------+------------------+
 *                        |
 *                        v
 *              Input to DISPCC block
 *              for DP pixel clock
 *
 */
static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{}

static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{}

static const struct clk_ops qmp_dp_pixel_clk_ops =;

static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{}

static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{}

static const struct clk_ops qmp_dp_link_clk_ops =;

static struct clk_hw *qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
{}

static int phy_dp_clks_register(struct qmp_combo *qmp, struct device_node *np)
{}

static struct clk_hw *qmp_combo_clk_hw_get(struct of_phandle_args *clkspec, void *data)
{}

static int qmp_combo_register_clocks(struct qmp_combo *qmp, struct device_node *usb_np,
					struct device_node *dp_np)
{}

#if IS_ENABLED(CONFIG_TYPEC)
static int qmp_combo_typec_switch_set(struct typec_switch_dev *sw,
				      enum typec_orientation orientation)
{}

static void qmp_combo_typec_unregister(void *data)
{}

static int qmp_combo_typec_switch_register(struct qmp_combo *qmp)
{}
#else
static int qmp_combo_typec_switch_register(struct qmp_combo *qmp)
{
	return 0;
}
#endif

static int qmp_combo_parse_dt_lecacy_dp(struct qmp_combo *qmp, struct device_node *np)
{}

static int qmp_combo_parse_dt_lecacy_usb(struct qmp_combo *qmp, struct device_node *np)
{}

static int qmp_combo_parse_dt_legacy(struct qmp_combo *qmp, struct device_node *usb_np,
					struct device_node *dp_np)
{}

static int qmp_combo_parse_dt(struct qmp_combo *qmp)
{}

static struct phy *qmp_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args)
{}

static int qmp_combo_probe(struct platform_device *pdev)
{}

static const struct of_device_id qmp_combo_of_match_table[] =;
MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table);

static struct platform_driver qmp_combo_driver =;

module_platform_driver();

MODULE_AUTHOR();
MODULE_DESCRIPTION();
MODULE_LICENSE();