linux/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2023, Linaro Limited
 */

#ifndef QCOM_PHY_QMP_PCS_UFS_V6_H_
#define QCOM_PHY_QMP_PCS_UFS_V6_H_

/* Only for QMP V6 PHY - UFS PCS registers */
#define QPHY_V6_PCS_UFS_PHY_START …
#define QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL …
#define QPHY_V6_PCS_UFS_SW_RESET …
#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB …
#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB …
#define QPHY_V6_PCS_UFS_PCS_CTRL1 …
#define QPHY_V6_PCS_UFS_PLL_CNTL …
#define QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL …
#define QPHY_V6_PCS_UFS_TX_SMALL_AMP_DRV_LVL …
#define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL …
#define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY …
#define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY …
#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY …
#define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL …
#define QPHY_V6_PCS_UFS_LINECFG_DISABLE …
#define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME …
#define QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2 …
#define QPHY_V6_PCS_UFS_TX_PWM_GEAR_BAND …
#define QPHY_V6_PCS_UFS_TX_HS_GEAR_BAND …
#define QPHY_V6_PCS_UFS_READY_STATUS …
#define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 …
#define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 …
#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME …
#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4 …
#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5 …
#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6 …
#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7 …

#endif