linux/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2023, Linaro Limited
 */

#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_
#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_

#define QSERDES_UFS_V6_TX_RES_CODE_LANE_TX
#define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX
#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX
#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX
#define QSERDES_UFS_V6_TX_LANE_MODE_1
#define QSERDES_UFS_V6_TX_FR_DCC_CTRL

#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4
#define QSERDES_UFS_V6_RX_UCDR_SO_SATURATION
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4
#define QSERDES_UFS_V6_RX_UCDR_PI_CTRL1
#define QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0
#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2
#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4
#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4
#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS
#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL
#define QSERDES_UFS_V6_RX_RX_EQU_ADAPTOR_CNTRL4
#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1
#define QSERDES_UFS_V6_RX_INTERFACE_MODE
#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B2
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B4
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6
#define QSERDES_UFS_V6_RX_MODE_RATE2_B3
#define QSERDES_UFS_V6_RX_MODE_RATE2_B6
#define QSERDES_UFS_V6_RX_MODE_RATE3_B3
#define QSERDES_UFS_V6_RX_MODE_RATE3_B4
#define QSERDES_UFS_V6_RX_MODE_RATE3_B5
#define QSERDES_UFS_V6_RX_MODE_RATE3_B8
#define QSERDES_UFS_V6_RX_MODE_RATE4_B0
#define QSERDES_UFS_V6_RX_MODE_RATE4_B1
#define QSERDES_UFS_V6_RX_MODE_RATE4_B2
#define QSERDES_UFS_V6_RX_MODE_RATE4_B3
#define QSERDES_UFS_V6_RX_MODE_RATE4_B4
#define QSERDES_UFS_V6_RX_MODE_RATE4_B6
#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL

#endif