// SPDX-License-Identifier: GPL-2.0-only #include <linux/clk.h> #include <linux/err.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> #include <linux/phy/phy.h> #include <linux/platform_device.h> #include <linux/delay.h> #include <linux/regmap.h> #include <linux/mfd/syscon.h> #include <linux/bitfield.h> /* USB QSCRATCH Hardware registers */ #define QSCRATCH_GENERAL_CFG … #define HSUSB_PHY_CTRL_REG … /* PHY_CTRL_REG */ #define HSUSB_CTRL_DMSEHV_CLAMP … #define HSUSB_CTRL_USB2_SUSPEND … #define HSUSB_CTRL_UTMI_CLK_EN … #define HSUSB_CTRL_UTMI_OTG_VBUS_VALID … #define HSUSB_CTRL_USE_CLKCORE … #define HSUSB_CTRL_DPSEHV_CLAMP … #define HSUSB_CTRL_COMMONONN … #define HSUSB_CTRL_ID_HV_CLAMP … #define HSUSB_CTRL_OTGSESSVLD_CLAMP … #define HSUSB_CTRL_CLAMP_EN … #define HSUSB_CTRL_RETENABLEN … #define HSUSB_CTRL_POR … /* QSCRATCH_GENERAL_CFG */ #define HSUSB_GCFG_XHCI_REV … /* USB QSCRATCH Hardware registers */ #define SSUSB_PHY_CTRL_REG … #define SSUSB_PHY_PARAM_CTRL_1 … #define SSUSB_PHY_PARAM_CTRL_2 … #define CR_PROTOCOL_DATA_IN_REG … #define CR_PROTOCOL_DATA_OUT_REG … #define CR_PROTOCOL_CAP_ADDR_REG … #define CR_PROTOCOL_CAP_DATA_REG … #define CR_PROTOCOL_READ_REG … #define CR_PROTOCOL_WRITE_REG … /* PHY_CTRL_REG */ #define SSUSB_CTRL_REF_USE_PAD … #define SSUSB_CTRL_TEST_POWERDOWN … #define SSUSB_CTRL_LANE0_PWR_PRESENT … #define SSUSB_CTRL_SS_PHY_EN … #define SSUSB_CTRL_SS_PHY_RESET … /* SSPHY control registers - Does this need 0x30? */ #define SSPHY_CTRL_RX_OVRD_IN_HI(lane) … #define SSPHY_CTRL_TX_OVRD_DRV_LO(lane) … /* SSPHY SoC version specific values */ #define SSPHY_RX_EQ_VALUE … /* Override value for transmit preemphasis */ #define SSPHY_TX_DEEMPH_3_5DB … /* Override value for mpll */ #define SSPHY_MPLL_VALUE … /* QSCRATCH PHY_PARAM_CTRL1 fields */ #define PHY_PARAM_CTRL1_TX_FULL_SWING_MASK … #define PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK … #define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK … #define PHY_PARAM_CTRL1_LOS_BIAS_MASK … #define PHY_PARAM_CTRL1_MASK … #define PHY_PARAM_CTRL1_TX_FULL_SWING(x) … #define PHY_PARAM_CTRL1_TX_DEEMPH_6DB(x) … #define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(x) … #define PHY_PARAM_CTRL1_LOS_BIAS(x) … /* RX OVRD IN HI bits */ #define RX_OVRD_IN_HI_RX_RESET_OVRD … #define RX_OVRD_IN_HI_RX_RX_RESET … #define RX_OVRD_IN_HI_RX_EQ_OVRD … #define RX_OVRD_IN_HI_RX_EQ_MASK … #define RX_OVRD_IN_HI_RX_EQ(x) … #define RX_OVRD_IN_HI_RX_EQ_EN_OVRD … #define RX_OVRD_IN_HI_RX_EQ_EN … #define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD … #define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK … #define RX_OVRD_IN_HI_RX_RATE_OVRD … #define RX_OVRD_IN_HI_RX_RATE_MASK … /* TX OVRD DRV LO register bits */ #define TX_OVRD_DRV_LO_AMPLITUDE_MASK … #define TX_OVRD_DRV_LO_PREEMPH_MASK … #define TX_OVRD_DRV_LO_PREEMPH(x) … #define TX_OVRD_DRV_LO_EN … /* MPLL bits */ #define SSPHY_MPLL_MASK … #define SSPHY_MPLL(x) … /* SS CAP register bits */ #define SS_CR_CAP_ADDR_REG … #define SS_CR_CAP_DATA_REG … #define SS_CR_READ_REG … #define SS_CR_WRITE_REG … #define LATCH_SLEEP … #define LATCH_TIMEOUT … struct usb_phy { … }; struct phy_drvdata { … }; /** * usb_phy_write_readback() - Write register and read back masked value to * confirm it is written * * @phy_dwc3: QCOM DWC3 phy context * @offset: register offset. * @mask: register bitmask specifying what should be updated * @val: value to write. */ static inline void usb_phy_write_readback(struct usb_phy *phy_dwc3, u32 offset, const u32 mask, u32 val) { … } static int wait_for_latch(void __iomem *addr) { … } /** * usb_ss_write_phycreg() - Write SSPHY register * * @phy_dwc3: QCOM DWC3 phy context * @addr: SSPHY address to write. * @val: value to write. */ static int usb_ss_write_phycreg(struct usb_phy *phy_dwc3, u32 addr, u32 val) { … } /** * usb_ss_read_phycreg() - Read SSPHY register. * * @phy_dwc3: QCOM DWC3 phy context * @addr: SSPHY address to read. * @val: pointer in which read is store. */ static int usb_ss_read_phycreg(struct usb_phy *phy_dwc3, u32 addr, u32 *val) { … } static int qcom_ipq806x_usb_hs_phy_init(struct phy *phy) { … } static int qcom_ipq806x_usb_hs_phy_exit(struct phy *phy) { … } static int qcom_ipq806x_usb_ss_phy_init(struct phy *phy) { … } static int qcom_ipq806x_usb_ss_phy_exit(struct phy *phy) { … } static const struct phy_drvdata qcom_ipq806x_usb_hs_drvdata = …; static const struct phy_drvdata qcom_ipq806x_usb_ss_drvdata = …; static const struct of_device_id qcom_ipq806x_usb_phy_table[] = …; MODULE_DEVICE_TABLE(of, qcom_ipq806x_usb_phy_table); static int qcom_ipq806x_usb_phy_probe(struct platform_device *pdev) { … } static struct platform_driver qcom_ipq806x_usb_phy_driver = …; module_platform_driver(…) …; MODULE_ALIAS(…) …; MODULE_LICENSE(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …;
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