// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (c) 2017 Rockchip Electronics Co. Ltd. * * Author: Zheng Yang <[email protected]> * Heiko Stuebner <[email protected]> */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/nvmem-consumer.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/phy/phy.h> #include <linux/slab.h> #define UPDATE(x, h, l) … /* REG: 0x00 */ #define RK3228_PRE_PLL_REFCLK_SEL_PCLK … /* REG: 0x01 */ #define RK3228_BYPASS_RXSENSE_EN … #define RK3228_BYPASS_PWRON_EN … #define RK3228_BYPASS_PLLPD_EN … /* REG: 0x02 */ #define RK3228_BYPASS_PDATA_EN … #define RK3228_PDATAEN_DISABLE … /* REG: 0x03 */ #define RK3228_BYPASS_AUTO_TERM_RES_CAL … #define RK3228_AUTO_TERM_RES_CAL_SPEED_14_8(x) … /* REG: 0x04 */ #define RK3228_AUTO_TERM_RES_CAL_SPEED_7_0(x) … /* REG: 0xaa */ #define RK3228_POST_PLL_CTRL_MANUAL … /* REG: 0xe0 */ #define RK3228_POST_PLL_POWER_DOWN … #define RK3228_PRE_PLL_POWER_DOWN … #define RK3228_RXSENSE_CLK_CH_ENABLE … #define RK3228_RXSENSE_DATA_CH2_ENABLE … #define RK3228_RXSENSE_DATA_CH1_ENABLE … #define RK3228_RXSENSE_DATA_CH0_ENABLE … /* REG: 0xe1 */ #define RK3228_BANDGAP_ENABLE … #define RK3228_TMDS_DRIVER_ENABLE … /* REG: 0xe2 */ #define RK3228_PRE_PLL_FB_DIV_8_MASK … #define RK3228_PRE_PLL_FB_DIV_8(x) … #define RK3228_PCLK_VCO_DIV_5_MASK … #define RK3228_PCLK_VCO_DIV_5(x) … #define RK3228_PRE_PLL_PRE_DIV_MASK … #define RK3228_PRE_PLL_PRE_DIV(x) … /* REG: 0xe3 */ #define RK3228_PRE_PLL_FB_DIV_7_0(x) … /* REG: 0xe4 */ #define RK3228_PRE_PLL_PCLK_DIV_B_MASK … #define RK3228_PRE_PLL_PCLK_DIV_B_SHIFT … #define RK3228_PRE_PLL_PCLK_DIV_B(x) … #define RK3228_PRE_PLL_PCLK_DIV_A_MASK … #define RK3228_PRE_PLL_PCLK_DIV_A(x) … /* REG: 0xe5 */ #define RK3228_PRE_PLL_PCLK_DIV_C_MASK … #define RK3228_PRE_PLL_PCLK_DIV_C(x) … #define RK3228_PRE_PLL_PCLK_DIV_D_MASK … #define RK3228_PRE_PLL_PCLK_DIV_D(x) … /* REG: 0xe6 */ #define RK3228_PRE_PLL_TMDSCLK_DIV_C_MASK … #define RK3228_PRE_PLL_TMDSCLK_DIV_C(x) … #define RK3228_PRE_PLL_TMDSCLK_DIV_A_MASK … #define RK3228_PRE_PLL_TMDSCLK_DIV_A(x) … #define RK3228_PRE_PLL_TMDSCLK_DIV_B_MASK … #define RK3228_PRE_PLL_TMDSCLK_DIV_B(x) … /* REG: 0xe8 */ #define RK3228_PRE_PLL_LOCK_STATUS … /* REG: 0xe9 */ #define RK3228_POST_PLL_POST_DIV_ENABLE … #define RK3228_POST_PLL_PRE_DIV_MASK … #define RK3228_POST_PLL_PRE_DIV(x) … /* REG: 0xea */ #define RK3228_POST_PLL_FB_DIV_7_0(x) … /* REG: 0xeb */ #define RK3228_POST_PLL_FB_DIV_8_MASK … #define RK3228_POST_PLL_FB_DIV_8(x) … #define RK3228_POST_PLL_POST_DIV_MASK … #define RK3228_POST_PLL_POST_DIV(x) … #define RK3228_POST_PLL_LOCK_STATUS … /* REG: 0xee */ #define RK3228_TMDS_CH_TA_ENABLE … /* REG: 0xef */ #define RK3228_TMDS_CLK_CH_TA(x) … #define RK3228_TMDS_DATA_CH2_TA(x) … #define RK3228_TMDS_DATA_CH1_TA(x) … #define RK3228_TMDS_DATA_CH0_TA(x) … /* REG: 0xf0 */ #define RK3228_TMDS_DATA_CH2_PRE_EMPHASIS_MASK … #define RK3228_TMDS_DATA_CH2_PRE_EMPHASIS(x) … #define RK3228_TMDS_DATA_CH1_PRE_EMPHASIS_MASK … #define RK3228_TMDS_DATA_CH1_PRE_EMPHASIS(x) … #define RK3228_TMDS_DATA_CH0_PRE_EMPHASIS_MASK … #define RK3228_TMDS_DATA_CH0_PRE_EMPHASIS(x) … /* REG: 0xf1 */ #define RK3228_TMDS_CLK_CH_OUTPUT_SWING(x) … #define RK3228_TMDS_DATA_CH2_OUTPUT_SWING(x) … /* REG: 0xf2 */ #define RK3228_TMDS_DATA_CH1_OUTPUT_SWING(x) … #define RK3228_TMDS_DATA_CH0_OUTPUT_SWING(x) … /* REG: 0x01 */ #define RK3328_BYPASS_RXSENSE_EN … #define RK3328_BYPASS_POWERON_EN … #define RK3328_BYPASS_PLLPD_EN … /* REG: 0x02 */ #define RK3328_INT_POL_HIGH … #define RK3328_BYPASS_PDATA_EN … #define RK3328_PDATA_EN … /* REG:0x05 */ #define RK3328_INT_TMDS_CLK(x) … #define RK3328_INT_TMDS_D2(x) … /* REG:0x07 */ #define RK3328_INT_TMDS_D1(x) … #define RK3328_INT_TMDS_D0(x) … /* for all RK3328_INT_TMDS_*, ESD_DET as defined in 0xc8-0xcb */ #define RK3328_INT_AGND_LOW_PULSE_LOCKED … #define RK3328_INT_RXSENSE_LOW_PULSE_LOCKED … #define RK3328_INT_VSS_AGND_ESD_DET … #define RK3328_INT_AGND_VSS_ESD_DET … /* REG: 0xa0 */ #define RK3328_PCLK_VCO_DIV_5_MASK … #define RK3328_PCLK_VCO_DIV_5(x) … #define RK3328_PRE_PLL_POWER_DOWN … /* REG: 0xa1 */ #define RK3328_PRE_PLL_PRE_DIV_MASK … #define RK3328_PRE_PLL_PRE_DIV(x) … /* REG: 0xa2 */ /* unset means center spread */ #define RK3328_SPREAD_SPECTRUM_MOD_DOWN … #define RK3328_SPREAD_SPECTRUM_MOD_DISABLE … #define RK3328_PRE_PLL_FRAC_DIV_DISABLE … #define RK3328_PRE_PLL_FB_DIV_11_8_MASK … #define RK3328_PRE_PLL_FB_DIV_11_8(x) … /* REG: 0xa3 */ #define RK3328_PRE_PLL_FB_DIV_7_0(x) … /* REG: 0xa4*/ #define RK3328_PRE_PLL_TMDSCLK_DIV_C_MASK … #define RK3328_PRE_PLL_TMDSCLK_DIV_C(x) … #define RK3328_PRE_PLL_TMDSCLK_DIV_B_MASK … #define RK3328_PRE_PLL_TMDSCLK_DIV_B(x) … #define RK3328_PRE_PLL_TMDSCLK_DIV_A_MASK … #define RK3328_PRE_PLL_TMDSCLK_DIV_A(x) … /* REG: 0xa5 */ #define RK3328_PRE_PLL_PCLK_DIV_B_SHIFT … #define RK3328_PRE_PLL_PCLK_DIV_B_MASK … #define RK3328_PRE_PLL_PCLK_DIV_B(x) … #define RK3328_PRE_PLL_PCLK_DIV_A_MASK … #define RK3328_PRE_PLL_PCLK_DIV_A(x) … /* REG: 0xa6 */ #define RK3328_PRE_PLL_PCLK_DIV_C_SHIFT … #define RK3328_PRE_PLL_PCLK_DIV_C_MASK … #define RK3328_PRE_PLL_PCLK_DIV_C(x) … #define RK3328_PRE_PLL_PCLK_DIV_D_MASK … #define RK3328_PRE_PLL_PCLK_DIV_D(x) … /* REG: 0xa9 */ #define RK3328_PRE_PLL_LOCK_STATUS … /* REG: 0xaa */ #define RK3328_POST_PLL_POST_DIV_ENABLE … #define RK3328_POST_PLL_REFCLK_SEL_TMDS … #define RK3328_POST_PLL_POWER_DOWN … /* REG:0xab */ #define RK3328_POST_PLL_FB_DIV_8(x) … #define RK3328_POST_PLL_PRE_DIV(x) … /* REG: 0xac */ #define RK3328_POST_PLL_FB_DIV_7_0(x) … /* REG: 0xad */ #define RK3328_POST_PLL_POST_DIV_MASK … #define RK3328_POST_PLL_POST_DIV_2 … #define RK3328_POST_PLL_POST_DIV_4 … #define RK3328_POST_PLL_POST_DIV_8 … /* REG: 0xaf */ #define RK3328_POST_PLL_LOCK_STATUS … /* REG: 0xb0 */ #define RK3328_BANDGAP_ENABLE … /* REG: 0xb2 */ #define RK3328_TMDS_CLK_DRIVER_EN … #define RK3328_TMDS_D2_DRIVER_EN … #define RK3328_TMDS_D1_DRIVER_EN … #define RK3328_TMDS_D0_DRIVER_EN … #define RK3328_TMDS_DRIVER_ENABLE … /* REG:0xc5 */ #define RK3328_BYPASS_TERM_RESISTOR_CALIB … #define RK3328_TERM_RESISTOR_CALIB_SPEED_14_8(x) … /* REG:0xc6 */ #define RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(x) … /* REG:0xc7 */ #define RK3328_TERM_RESISTOR_50 … #define RK3328_TERM_RESISTOR_62_5 … #define RK3328_TERM_RESISTOR_75 … #define RK3328_TERM_RESISTOR_100 … /* REG 0xc8 - 0xcb */ #define RK3328_ESD_DETECT_MASK … #define RK3328_ESD_DETECT_340MV … #define RK3328_ESD_DETECT_280MV … #define RK3328_ESD_DETECT_260MV … #define RK3328_ESD_DETECT_240MV … /* resistors can be used in parallel */ #define RK3328_TMDS_TERM_RESIST_MASK … #define RK3328_TMDS_TERM_RESIST_75 … #define RK3328_TMDS_TERM_RESIST_150 … #define RK3328_TMDS_TERM_RESIST_300 … #define RK3328_TMDS_TERM_RESIST_600 … #define RK3328_TMDS_TERM_RESIST_1000 … #define RK3328_TMDS_TERM_RESIST_2000 … /* REG: 0xd1 */ #define RK3328_PRE_PLL_FRAC_DIV_23_16(x) … /* REG: 0xd2 */ #define RK3328_PRE_PLL_FRAC_DIV_15_8(x) … /* REG: 0xd3 */ #define RK3328_PRE_PLL_FRAC_DIV_7_0(x) … struct inno_hdmi_phy_drv_data; struct inno_hdmi_phy { … }; struct pre_pll_config { … }; struct post_pll_config { … }; struct phy_config { … }; struct inno_hdmi_phy_ops { … }; struct inno_hdmi_phy_drv_data { … }; static const struct pre_pll_config pre_pll_cfg_table[] = …; static const struct post_pll_config post_pll_cfg_table[] = …; /* phy tuning values for an undocumented set of registers */ static const struct phy_config rk3228_phy_cfg[] = …; /* phy tuning values for an undocumented set of registers */ static const struct phy_config rk3328_phy_cfg[] = …; static inline struct inno_hdmi_phy *to_inno_hdmi_phy(struct clk_hw *hw) { … } /* * The register description of the IP block does not use any distinct names * but instead the databook simply numbers the registers in one-increments. * As the registers are obviously 32bit sized, the inno_* functions * translate the databook register names to the actual registers addresses. */ static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val) { … } static inline u8 inno_read(struct inno_hdmi_phy *inno, u32 reg) { … } static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg, u8 mask, u8 val) { … } #define inno_poll(inno, reg, val, cond, sleep_us, timeout_us) … static unsigned long inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno, unsigned long rate) { … } static irqreturn_t inno_hdmi_phy_rk3328_hardirq(int irq, void *dev_id) { … } static irqreturn_t inno_hdmi_phy_rk3328_irq(int irq, void *dev_id) { … } static int inno_hdmi_phy_power_on(struct phy *phy) { … } static int inno_hdmi_phy_power_off(struct phy *phy) { … } static const struct phy_ops inno_hdmi_phy_ops = …; static const struct pre_pll_config *inno_hdmi_phy_get_pre_pll_cfg(struct inno_hdmi_phy *inno, unsigned long rate) { … } static int inno_hdmi_phy_rk3228_clk_is_prepared(struct clk_hw *hw) { … } static int inno_hdmi_phy_rk3228_clk_prepare(struct clk_hw *hw) { … } static void inno_hdmi_phy_rk3228_clk_unprepare(struct clk_hw *hw) { … } static unsigned long inno_hdmi_phy_rk3228_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static long inno_hdmi_phy_rk3228_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { … } static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static const struct clk_ops inno_hdmi_phy_rk3228_clk_ops = …; static int inno_hdmi_phy_rk3328_clk_is_prepared(struct clk_hw *hw) { … } static int inno_hdmi_phy_rk3328_clk_prepare(struct clk_hw *hw) { … } static void inno_hdmi_phy_rk3328_clk_unprepare(struct clk_hw *hw) { … } static unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static long inno_hdmi_phy_rk3328_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { … } static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static const struct clk_ops inno_hdmi_phy_rk3328_clk_ops = …; static int inno_hdmi_phy_clk_register(struct inno_hdmi_phy *inno) { … } static int inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno) { … } static int inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy *inno, const struct post_pll_config *cfg, const struct phy_config *phy_cfg) { … } static void inno_hdmi_phy_rk3228_power_off(struct inno_hdmi_phy *inno) { … } static const struct inno_hdmi_phy_ops rk3228_hdmi_phy_ops = …; static int inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno) { … } static int inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, const struct post_pll_config *cfg, const struct phy_config *phy_cfg) { … } static void inno_hdmi_phy_rk3328_power_off(struct inno_hdmi_phy *inno) { … } static const struct inno_hdmi_phy_ops rk3328_hdmi_phy_ops = …; static const struct inno_hdmi_phy_drv_data rk3228_hdmi_phy_drv_data = …; static const struct inno_hdmi_phy_drv_data rk3328_hdmi_phy_drv_data = …; static const struct regmap_config inno_hdmi_phy_regmap_config = …; static void inno_hdmi_phy_action(void *data) { … } static int inno_hdmi_phy_probe(struct platform_device *pdev) { … } static void inno_hdmi_phy_remove(struct platform_device *pdev) { … } static const struct of_device_id inno_hdmi_phy_of_match[] = …; MODULE_DEVICE_TABLE(of, inno_hdmi_phy_of_match); static struct platform_driver inno_hdmi_phy_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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