// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Author: Chris Zhong <[email protected]> * Kever Yang <[email protected]> * * The ROCKCHIP Type-C PHY has two PLL clocks. The first PLL clock * is used for USB3, the second PLL clock is used for DP. This Type-C PHY has * 3 working modes: USB3 only mode, DP only mode, and USB3+DP mode. * At USB3 only mode, both PLL clocks need to be initialized, this allows the * PHY to switch mode between USB3 and USB3+DP, without disconnecting the USB * device. * In The DP only mode, only the DP PLL needs to be powered on, and the 4 lanes * are all used for DP. * * This driver gets extcon cable state and property, then decides which mode to * select: * * 1. USB3 only mode: * EXTCON_USB or EXTCON_USB_HOST state is true, and * EXTCON_PROP_USB_SS property is true. * EXTCON_DISP_DP state is false. * * 2. DP only mode: * EXTCON_DISP_DP state is true, and * EXTCON_PROP_USB_SS property is false. * If EXTCON_USB_HOST state is true, it is DP + USB2 mode, since the USB2 phy * is a separate phy, so this case is still DP only mode. * * 3. USB3+DP mode: * EXTCON_USB_HOST and EXTCON_DISP_DP are both true, and * EXTCON_PROP_USB_SS property is true. * * This Type-C PHY driver supports normal and flip orientation. The orientation * is reported by the EXTCON_PROP_USB_TYPEC_POLARITY property: true is flip * orientation, false is normal orientation. */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/extcon.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/mutex.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/reset.h> #include <linux/mfd/syscon.h> #include <linux/phy/phy.h> #define CMN_SSM_BANDGAP … #define CMN_SSM_BIAS … #define CMN_PLLSM0_PLLEN … #define CMN_PLLSM0_PLLPRE … #define CMN_PLLSM0_PLLVREF … #define CMN_PLLSM0_PLLLOCK … #define CMN_PLLSM1_PLLEN … #define CMN_PLLSM1_PLLPRE … #define CMN_PLLSM1_PLLVREF … #define CMN_PLLSM1_PLLLOCK … #define CMN_PLLSM1_USER_DEF_CTRL … #define CMN_ICAL_OVRD … #define CMN_PLL0_VCOCAL_OVRD … #define CMN_PLL0_VCOCAL_INIT … #define CMN_PLL0_VCOCAL_ITER … #define CMN_PLL0_LOCK_REFCNT_START … #define CMN_PLL0_LOCK_PLLCNT_START … #define CMN_PLL0_LOCK_PLLCNT_THR … #define CMN_PLL0_INTDIV … #define CMN_PLL0_FRACDIV … #define CMN_PLL0_HIGH_THR … #define CMN_PLL0_DSM_DIAG … #define CMN_PLL0_SS_CTRL1 … #define CMN_PLL0_SS_CTRL2 … #define CMN_PLL1_VCOCAL_START … #define CMN_PLL1_VCOCAL_OVRD … #define CMN_PLL1_VCOCAL_INIT … #define CMN_PLL1_VCOCAL_ITER … #define CMN_PLL1_LOCK_REFCNT_START … #define CMN_PLL1_LOCK_PLLCNT_START … #define CMN_PLL1_LOCK_PLLCNT_THR … #define CMN_PLL1_INTDIV … #define CMN_PLL1_FRACDIV … #define CMN_PLL1_HIGH_THR … #define CMN_PLL1_DSM_DIAG … #define CMN_PLL1_SS_CTRL1 … #define CMN_PLL1_SS_CTRL2 … #define CMN_RXCAL_OVRD … #define CMN_TXPUCAL_CTRL … #define CMN_TXPUCAL_OVRD … #define CMN_TXPDCAL_CTRL … #define CMN_TXPDCAL_OVRD … /* For CMN_TXPUCAL_CTRL, CMN_TXPDCAL_CTRL */ #define CMN_TXPXCAL_START … #define CMN_TXPXCAL_DONE … #define CMN_TXPXCAL_NO_RESPONSE … #define CMN_TXPXCAL_CURRENT_RESPONSE … #define CMN_TXPU_ADJ_CTRL … #define CMN_TXPD_ADJ_CTRL … /* * For CMN_TXPUCAL_CTRL, CMN_TXPDCAL_CTRL, * CMN_TXPU_ADJ_CTRL, CMN_TXPDCAL_CTRL * * NOTE: some of these registers are documented to be 2's complement * signed numbers, but then documented to be always positive. Weird. * In such a case, using CMN_CALIB_CODE_POS() avoids the unnecessary * sign extension. */ #define CMN_CALIB_CODE_WIDTH … #define CMN_CALIB_CODE_OFFSET … #define CMN_CALIB_CODE_MASK … #define CMN_CALIB_CODE(x) … #define CMN_CALIB_CODE_POS_MASK … #define CMN_CALIB_CODE_POS(x) … #define CMN_DIAG_PLL0_FBH_OVRD … #define CMN_DIAG_PLL0_FBL_OVRD … #define CMN_DIAG_PLL0_OVRD … #define CMN_DIAG_PLL0_V2I_TUNE … #define CMN_DIAG_PLL0_CP_TUNE … #define CMN_DIAG_PLL0_LF_PROG … #define CMN_DIAG_PLL1_FBH_OVRD … #define CMN_DIAG_PLL1_FBL_OVRD … #define CMN_DIAG_PLL1_OVRD … #define CMN_DIAG_PLL1_V2I_TUNE … #define CMN_DIAG_PLL1_CP_TUNE … #define CMN_DIAG_PLL1_LF_PROG … #define CMN_DIAG_PLL1_PTATIS_TUNE1 … #define CMN_DIAG_PLL1_PTATIS_TUNE2 … #define CMN_DIAG_PLL1_INCLK_CTRL … #define CMN_DIAG_HSCLK_SEL … #define XCVR_PSM_RCTRL(n) … #define XCVR_PSM_CAL_TMR(n) … #define XCVR_PSM_A0IN_TMR(n) … #define TX_TXCC_CAL_SCLR_MULT(n) … #define TX_TXCC_CPOST_MULT_00(n) … #define TX_TXCC_CPOST_MULT_01(n) … #define TX_TXCC_CPOST_MULT_10(n) … #define TX_TXCC_CPOST_MULT_11(n) … #define TX_TXCC_MGNFS_MULT_000(n) … #define TX_TXCC_MGNFS_MULT_001(n) … #define TX_TXCC_MGNFS_MULT_010(n) … #define TX_TXCC_MGNFS_MULT_011(n) … #define TX_TXCC_MGNFS_MULT_100(n) … #define TX_TXCC_MGNFS_MULT_101(n) … #define TX_TXCC_MGNFS_MULT_110(n) … #define TX_TXCC_MGNFS_MULT_111(n) … #define TX_TXCC_MGNLS_MULT_000(n) … #define TX_TXCC_MGNLS_MULT_001(n) … #define TX_TXCC_MGNLS_MULT_010(n) … #define TX_TXCC_MGNLS_MULT_011(n) … #define TX_TXCC_MGNLS_MULT_100(n) … #define TX_TXCC_MGNLS_MULT_101(n) … #define TX_TXCC_MGNLS_MULT_110(n) … #define TX_TXCC_MGNLS_MULT_111(n) … #define XCVR_DIAG_PLLDRC_CTRL(n) … #define XCVR_DIAG_BIDI_CTRL(n) … #define XCVR_DIAG_LANE_FCM_EN_MGN(n) … #define TX_PSC_A0(n) … #define TX_PSC_A1(n) … #define TX_PSC_A2(n) … #define TX_PSC_A3(n) … #define TX_RCVDET_CTRL(n) … #define TX_RCVDET_EN_TMR(n) … #define TX_RCVDET_ST_TMR(n) … #define TX_DIAG_TX_DRV(n) … #define TX_DIAG_BGREF_PREDRV_DELAY … /* Use this for "n" in macros like "_MULT_XXX" to target the aux channel */ #define AUX_CH_LANE … #define TX_ANA_CTRL_REG_1 … #define TXDA_DP_AUX_EN … #define AUXDA_SE_EN … #define TXDA_CAL_LATCH_EN … #define AUXDA_POLARITY … #define TXDA_DRV_POWER_ISOLATION_EN … #define TXDA_DRV_POWER_EN_PH_2_N … #define TXDA_DRV_POWER_EN_PH_1_N … #define TXDA_BGREF_EN … #define TXDA_DRV_LDO_EN … #define TXDA_DECAP_EN_DEL … #define TXDA_DECAP_EN … #define TXDA_UPHY_SUPPLY_EN_DEL … #define TXDA_UPHY_SUPPLY_EN … #define TXDA_LOW_LEAKAGE_EN … #define TXDA_DRV_IDLE_LOWI_EN … #define TXDA_DRV_CMN_MODE_EN … #define TX_ANA_CTRL_REG_2 … #define AUXDA_DEBOUNCING_CLK … #define TXDA_LPBK_RECOVERED_CLK_EN … #define TXDA_LPBK_ISI_GEN_EN … #define TXDA_LPBK_SERIAL_EN … #define TXDA_LPBK_LINE_EN … #define TXDA_DRV_LDO_REDC_SINKIQ … #define XCVR_DECAP_EN_DEL … #define XCVR_DECAP_EN … #define TXDA_MPHY_ENABLE_HS_NT … #define TXDA_MPHY_SA_MODE … #define TXDA_DRV_LDO_RBYR_FB_EN … #define TXDA_DRV_RST_PULL_DOWN … #define TXDA_DRV_LDO_BG_FB_EN … #define TXDA_DRV_LDO_BG_REF_EN … #define TXDA_DRV_PREDRV_EN_DEL … #define TXDA_DRV_PREDRV_EN … #define TXDA_COEFF_CALC_CTRL … #define TX_HIGH_Z … #define TX_VMARGIN_OFFSET … #define TX_VMARGIN_MASK … #define LOW_POWER_SWING_EN … #define TX_FCM_DRV_MAIN_EN … #define TX_FCM_FULL_MARGIN … #define TX_DIG_CTRL_REG_2 … #define TX_HIGH_Z_TM_EN … #define TX_RESCAL_CODE_OFFSET … #define TX_RESCAL_CODE_MASK … #define TXDA_CYA_AUXDA_CYA … #define TX_ANA_CTRL_REG_3 … #define TX_ANA_CTRL_REG_4 … #define TX_ANA_CTRL_REG_5 … #define RX_PSC_A0(n) … #define RX_PSC_A1(n) … #define RX_PSC_A2(n) … #define RX_PSC_A3(n) … #define RX_PSC_CAL(n) … #define RX_PSC_RDY(n) … #define RX_IQPI_ILL_CAL_OVRD … #define RX_EPI_ILL_CAL_OVRD … #define RX_SDCAL0_OVRD … #define RX_SDCAL1_OVRD … #define RX_SLC_INIT … #define RX_SLC_RUN … #define RX_CDRLF_CNFG2 … #define RX_SIGDET_HL_FILT_TMR(n) … #define RX_SLC_IOP0_OVRD … #define RX_SLC_IOP1_OVRD … #define RX_SLC_QOP0_OVRD … #define RX_SLC_QOP1_OVRD … #define RX_SLC_EOP0_OVRD … #define RX_SLC_EOP1_OVRD … #define RX_SLC_ION0_OVRD … #define RX_SLC_ION1_OVRD … #define RX_SLC_QON0_OVRD … #define RX_SLC_QON1_OVRD … #define RX_SLC_EON0_OVRD … #define RX_SLC_EON1_OVRD … #define RX_SLC_IEP0_OVRD … #define RX_SLC_IEP1_OVRD … #define RX_SLC_QEP0_OVRD … #define RX_SLC_QEP1_OVRD … #define RX_SLC_EEP0_OVRD … #define RX_SLC_EEP1_OVRD … #define RX_SLC_IEN0_OVRD … #define RX_SLC_IEN1_OVRD … #define RX_SLC_QEN0_OVRD … #define RX_SLC_QEN1_OVRD … #define RX_SLC_EEN0_OVRD … #define RX_SLC_EEN1_OVRD … #define RX_REE_CTRL_DATA_MASK(n) … #define RX_DIAG_SIGDET_TUNE(n) … #define RX_DIAG_SC2C_DELAY … #define PMA_LANE_CFG … #define PIPE_CMN_CTRL1 … #define PIPE_CMN_CTRL2 … #define PIPE_COM_LOCK_CFG1 … #define PIPE_COM_LOCK_CFG2 … #define PIPE_RCV_DET_INH … #define DP_MODE_CTL … #define DP_CLK_CTL … #define STS … #define PHY_ISO_CMN_CTRL … #define PHY_DP_TX_CTL … #define PMA_CMN_CTRL1 … #define PHY_PMA_ISO_CMN_CTRL … #define PHY_ISOLATION_CTRL … #define PHY_PMA_ISO_XCVR_CTRL(n) … #define PHY_PMA_ISO_LINK_MODE(n) … #define PHY_PMA_ISO_PWRST_CTRL(n) … #define PHY_PMA_ISO_TX_DATA_LO(n) … #define PHY_PMA_ISO_TX_DATA_HI(n) … #define PHY_PMA_ISO_RX_DATA_LO(n) … #define PHY_PMA_ISO_RX_DATA_HI(n) … #define TX_BIST_CTRL(n) … #define TX_BIST_UDDWR(n) … /* * Selects which PLL clock will be driven on the analog high speed * clock 0: PLL 0 div 1 * clock 1: PLL 1 div 2 */ #define CLK_PLL_CONFIG … #define CLK_PLL_MASK … #define CMN_READY … #define DP_PLL_CLOCK_ENABLE … #define DP_PLL_ENABLE … #define DP_PLL_DATA_RATE_RBR … #define DP_PLL_DATA_RATE_HBR … #define DP_PLL_DATA_RATE_HBR2 … #define DP_MODE_A0 … #define DP_MODE_A2 … #define DP_MODE_ENTER_A0 … #define DP_MODE_ENTER_A2 … #define PHY_MODE_SET_TIMEOUT … #define PIN_ASSIGN_C_E … #define PIN_ASSIGN_D_F … #define MODE_DISCONNECT … #define MODE_UFP_USB … #define MODE_DFP_USB … #define MODE_DFP_DP … struct usb3phy_reg { … }; /** * struct rockchip_usb3phy_port_cfg - usb3-phy port configuration. * @reg: the base address for usb3-phy config. * @typec_conn_dir: the register of type-c connector direction. * @usb3tousb2_en: the register of type-c force usb2 to usb2 enable. * @external_psm: the register of type-c phy external psm clock. * @pipe_status: the register of type-c phy pipe status. * @usb3_host_disable: the register of type-c usb3 host disable. * @usb3_host_port: the register of type-c usb3 host port. * @uphy_dp_sel: the register of type-c phy DP select control. */ struct rockchip_usb3phy_port_cfg { … }; struct rockchip_typec_phy { … }; struct phy_reg { … }; static struct phy_reg usb3_pll_cfg[] = …; static struct phy_reg dp_pll_cfg[] = …; static const struct rockchip_usb3phy_port_cfg rk3399_usb3phy_port_cfgs[] = …; static void tcphy_cfg_24m(struct rockchip_typec_phy *tcphy) { … } static void tcphy_cfg_usb3_pll(struct rockchip_typec_phy *tcphy) { … } static void tcphy_cfg_dp_pll(struct rockchip_typec_phy *tcphy) { … } static void tcphy_tx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane) { … } static void tcphy_rx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane) { … } static void tcphy_dp_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane) { … } static inline int property_enable(struct rockchip_typec_phy *tcphy, const struct usb3phy_reg *reg, bool en) { … } static void tcphy_dp_aux_set_flip(struct rockchip_typec_phy *tcphy) { … } static void tcphy_dp_aux_calibration(struct rockchip_typec_phy *tcphy) { … } static int tcphy_phy_init(struct rockchip_typec_phy *tcphy, u8 mode) { … } static void tcphy_phy_deinit(struct rockchip_typec_phy *tcphy) { … } static int tcphy_get_mode(struct rockchip_typec_phy *tcphy) { … } static int tcphy_cfg_usb3_to_usb2_only(struct rockchip_typec_phy *tcphy, bool value) { … } static int rockchip_usb3_phy_power_on(struct phy *phy) { … } static int rockchip_usb3_phy_power_off(struct phy *phy) { … } static const struct phy_ops rockchip_usb3_phy_ops = …; static int rockchip_dp_phy_power_on(struct phy *phy) { … } static int rockchip_dp_phy_power_off(struct phy *phy) { … } static const struct phy_ops rockchip_dp_phy_ops = …; static int tcphy_parse_dt(struct rockchip_typec_phy *tcphy, struct device *dev) { … } static void typec_phy_pre_init(struct rockchip_typec_phy *tcphy) { … } static int rockchip_typec_phy_probe(struct platform_device *pdev) { … } static void rockchip_typec_phy_remove(struct platform_device *pdev) { … } static const struct of_device_id rockchip_typec_phy_dt_ids[] = …; MODULE_DEVICE_TABLE(of, rockchip_typec_phy_dt_ids); static struct platform_driver rockchip_typec_phy_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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