// SPDX-License-Identifier: GPL-2.0 /* * Rockchip MIPI RX Innosilicon DPHY driver * * Copyright (C) 2021 Fuzhou Rockchip Electronics Co., Ltd. */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_platform.h> #include <linux/phy/phy.h> #include <linux/phy/phy-mipi-dphy.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/reset.h> /* GRF */ #define RK1808_GRF_PD_VI_CON_OFFSET … #define RK3326_GRF_PD_VI_CON_OFFSET … #define RK3368_GRF_SOC_CON6_OFFSET … #define RK3568_GRF_VI_CON0 … #define RK3568_GRF_VI_CON1 … /* PHY */ #define CSIDPHY_CTRL_LANE_ENABLE … #define CSIDPHY_CTRL_LANE_ENABLE_CK … #define CSIDPHY_CTRL_LANE_ENABLE_MASK … #define CSIDPHY_CTRL_LANE_ENABLE_UNDEFINED … /* not present on all variants */ #define CSIDPHY_CTRL_PWRCTL … #define CSIDPHY_CTRL_PWRCTL_UNDEFINED … #define CSIDPHY_CTRL_PWRCTL_SYNCRST … #define CSIDPHY_CTRL_PWRCTL_LDO_PD … #define CSIDPHY_CTRL_PWRCTL_PLL_PD … #define CSIDPHY_CTRL_DIG_RST … #define CSIDPHY_CTRL_DIG_RST_UNDEFINED … #define CSIDPHY_CTRL_DIG_RST_RESET … /* offset after ths_settle_offset */ #define CSIDPHY_CLK_THS_SETTLE … #define CSIDPHY_LANE_THS_SETTLE(n) … #define CSIDPHY_THS_SETTLE_MASK … /* offset after calib_offset */ #define CSIDPHY_CLK_CALIB_EN … #define CSIDPHY_LANE_CALIB_EN(n) … #define CSIDPHY_CALIB_EN … /* Configure the count time of the THS-SETTLE by protocol. */ #define RK1808_CSIDPHY_CLK_WR_THS_SETTLE … #define RK3326_CSIDPHY_CLK_WR_THS_SETTLE … #define RK3368_CSIDPHY_CLK_WR_THS_SETTLE … #define RK3568_CSIDPHY_CLK_WR_THS_SETTLE … /* Calibration reception enable */ #define RK1808_CSIDPHY_CLK_CALIB_EN … #define RK3568_CSIDPHY_CLK_CALIB_EN … /* * The higher 16-bit of this register is used for write protection * only if BIT(x + 16) set to 1 the BIT(x) can be written. */ #define HIWORD_UPDATE(val, mask, shift) … #define HZ_TO_MHZ(freq) … enum dphy_reg_id { … }; struct dphy_reg { … }; #define PHY_REG(_offset, _width, _shift) … static const struct dphy_reg rk1808_grf_dphy_regs[] = …; static const struct dphy_reg rk3326_grf_dphy_regs[] = …; static const struct dphy_reg rk3368_grf_dphy_regs[] = …; static const struct dphy_reg rk3568_grf_dphy_regs[] = …; struct hsfreq_range { … }; struct dphy_drv_data { … }; struct rockchip_inno_csidphy { … }; static inline void write_grf_reg(struct rockchip_inno_csidphy *priv, int index, u8 value) { … } /* These tables must be sorted by .range_h ascending. */ static const struct hsfreq_range rk1808_mipidphy_hsfreq_ranges[] = …; static const struct hsfreq_range rk3326_mipidphy_hsfreq_ranges[] = …; static const struct hsfreq_range rk3368_mipidphy_hsfreq_ranges[] = …; static void rockchip_inno_csidphy_ths_settle(struct rockchip_inno_csidphy *priv, int hsfreq, int offset) { … } static int rockchip_inno_csidphy_configure(struct phy *phy, union phy_configure_opts *opts) { … } static int rockchip_inno_csidphy_power_on(struct phy *phy) { … } static int rockchip_inno_csidphy_power_off(struct phy *phy) { … } static int rockchip_inno_csidphy_init(struct phy *phy) { … } static int rockchip_inno_csidphy_exit(struct phy *phy) { … } static const struct phy_ops rockchip_inno_csidphy_ops = …; static const struct dphy_drv_data rk1808_mipidphy_drv_data = …; static const struct dphy_drv_data rk3326_mipidphy_drv_data = …; static const struct dphy_drv_data rk3368_mipidphy_drv_data = …; static const struct dphy_drv_data rk3568_mipidphy_drv_data = …; static const struct of_device_id rockchip_inno_csidphy_match_id[] = …; MODULE_DEVICE_TABLE(of, rockchip_inno_csidphy_match_id); static int rockchip_inno_csidphy_probe(struct platform_device *pdev) { … } static void rockchip_inno_csidphy_remove(struct platform_device *pdev) { … } static struct platform_driver rockchip_inno_csidphy_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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