linux/drivers/phy/samsung/phy-exynos-pcie.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Samsung Exynos SoC series PCIe PHY driver
 *
 * Phy provider for PCIe controller on Exynos SoC series
 *
 * Copyright (C) 2017-2020 Samsung Electronics Co., Ltd.
 * Jaehoon Chung <[email protected]>
 */

#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/phy/phy.h>
#include <linux/regmap.h>

#define PCIE_PHY_OFFSET(x) …

/* Sysreg FSYS register offsets and bits for Exynos5433 */
#define PCIE_EXYNOS5433_PHY_MAC_RESET …
#define PCIE_MAC_RESET_MASK …
#define PCIE_MAC_RESET …
#define PCIE_EXYNOS5433_PHY_L1SUB_CM_CON …
#define PCIE_REFCLK_GATING_EN …
#define PCIE_EXYNOS5433_PHY_COMMON_RESET …
#define PCIE_PHY_RESET …
#define PCIE_EXYNOS5433_PHY_GLOBAL_RESET …
#define PCIE_GLOBAL_RESET …
#define PCIE_REFCLK …
#define PCIE_REFCLK_MASK …
#define PCIE_APP_REQ_EXIT_L1_MODE …

/* PMU PCIE PHY isolation control */
#define EXYNOS5433_PMU_PCIE_PHY_OFFSET …

/* For Exynos pcie phy */
struct exynos_pcie_phy { … };

static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
{ … }

/* Exynos5433 specific functions */
static int exynos5433_pcie_phy_init(struct phy *phy)
{ … }

static int exynos5433_pcie_phy_exit(struct phy *phy)
{ … }

static const struct phy_ops exynos5433_phy_ops = …;

static const struct of_device_id exynos_pcie_phy_match[] = …;

static int exynos_pcie_phy_probe(struct platform_device *pdev)
{ … }

static struct platform_driver exynos_pcie_phy_driver = …;
builtin_platform_driver(…) …;