linux/drivers/phy/samsung/phy-samsung-ufs.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * UFS PHY driver for Samsung EXYNOS SoC
 *
 * Copyright (C) 2020 Samsung Electronics Co., Ltd.
 * Author: Seungwon Jeon <[email protected]>
 * Author: Alim Akhtar <[email protected]>
 *
 */
#ifndef _PHY_SAMSUNG_UFS_
#define _PHY_SAMSUNG_UFS_

#include <linux/phy/phy.h>
#include <linux/regmap.h>

#define PHY_COMN_BLK …
#define PHY_TRSV_BLK …
#define END_UFS_PHY_CFG …
#define PHY_TRSV_CH_OFFSET …
#define PHY_APB_ADDR(off) …

#define PHY_COMN_REG_CFG(o, v, d) …

#define PHY_TRSV_REG_CFG_OFFSET(o, v, d, c) …

#define PHY_TRSV_REG_CFG(o, v, d) …

/* UFS PHY registers */
#define PHY_PLL_LOCK_STATUS …

#define PHY_PLL_LOCK_BIT …
#define PHY_CDR_LOCK_BIT …

/* description for PHY calibration */
enum { … };

#define PWR_MODE_HS_G1_ANY …
#define PWR_MODE_HS_G1_SER_A …
#define PWR_MODE_HS_G1_SER_B …
#define PWR_MODE_HS_G2_ANY …
#define PWR_MODE_HS_G2_SER_A …
#define PWR_MODE_HS_G2_SER_B …
#define PWR_MODE_HS_G3_ANY …
#define PWR_MODE_HS_G3_SER_A …
#define PWR_MODE_HS_G3_SER_B …
#define PWR_MODE(g, s, m) …
#define PWR_MODE_PWM_ANY …
#define PWR_MODE_HS(g, s) …
#define PWR_MODE_HS_ANY …
#define PWR_MODE_ANY …
/* PHY calibration point/state */
enum { … };

struct samsung_ufs_phy_cfg { … };

struct samsung_ufs_phy_pmu_isol { … };

struct samsung_ufs_phy_drvdata { … };

struct samsung_ufs_phy { … };

static inline struct samsung_ufs_phy *get_samsung_ufs_phy(struct phy *phy)
{ … }

static inline void samsung_ufs_phy_ctrl_isol(
		struct samsung_ufs_phy *phy, u32 isol)
{ … }

int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy, u8 lane);

extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy;
extern const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy;
extern const struct samsung_ufs_phy_drvdata fsd_ufs_phy;
extern const struct samsung_ufs_phy_drvdata tensor_gs101_ufs_phy;

#endif /* _PHY_SAMSUNG_UFS_ */